arm/mach-omap2/omap-headsmp.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Secondary CPU startup routine source file.
0004  *
0005  * Copyright (C) 2009-2014 Texas Instruments, Inc.
0006  *
0007  * Author:
0008  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
0009  *
0010  * Interface functions needed for the SMP. This file is based on arm
0011  * realview smp platform.
0012  * Copyright (c) 2003 ARM Limited.
0013  */
0014
0015 #include <linux/linkage.h>
0016 #include <linux/init.h>
0017 #include <asm/assembler.h>
0018
0019 #include "omap44xx.h"
0020
0021 /* Physical address needed since MMU not enabled yet on secondary core */
0022 #define AUX_CORE_BOOT0_PA           0x48281800
0023 #define API_HYP_ENTRY               0x102
0024
0025 ENTRY(omap_secondary_startup)
0026 #ifdef CONFIG_SMP
0027     b   secondary_startup
0028 #else
0029 /* Should never get here */
0030 again:  wfi
0031     b   again
0032 #endif
0033 #ENDPROC(omap_secondary_startup)
0034
0035 /*
0036  * OMAP5 specific entry point for secondary CPU to jump from ROM
0037  * code.  This routine also provides a holding flag into which
0038  * secondary core is held until we're ready for it to initialise.
0039  * The primary core will update this flag using a hardware
0040  * register AuxCoreBoot0.
0041  */
0042 ENTRY(omap5_secondary_startup)
0043 wait:   ldr r2, =AUX_CORE_BOOT0_PA  @ read from AuxCoreBoot0
0044     ldr r0, [r2]
0045     mov r0, r0, lsr #5
0046     mrc p15, 0, r4, c0, c0, 5
0047     and r4, r4, #0x0f
0048     cmp r0, r4
0049     bne wait
0050     b   omap_secondary_startup
0051 ENDPROC(omap5_secondary_startup)
0052 /*
0053  * Same as omap5_secondary_startup except we call into the ROM to
0054  * enable HYP mode first.  This is called instead of
0055  * omap5_secondary_startup if the primary CPU was put into HYP mode by
0056  * the boot loader.
0057  */
0058     .arch armv7-a
0059     .arch_extension sec
0060 ENTRY(omap5_secondary_hyp_startup)
0061 wait_2: ldr r2, =AUX_CORE_BOOT0_PA  @ read from AuxCoreBoot0
0062     ldr r0, [r2]
0063     mov r0, r0, lsr #5
0064     mrc p15, 0, r4, c0, c0, 5
0065     and r4, r4, #0x0f
0066     cmp r0, r4
0067     bne wait_2
0068     ldr r12, =API_HYP_ENTRY
0069     badr    r0, hyp_boot
0070     smc #0
0071 hyp_boot:
0072     b   omap_secondary_startup
0073 ENDPROC(omap5_secondary_hyp_startup)
0074 /*
0075  * OMAP4 specific entry point for secondary CPU to jump from ROM
0076  * code.  This routine also provides a holding flag into which
0077  * secondary core is held until we're ready for it to initialise.
0078  * The primary core will update this flag using a hardware
0079  * register AuxCoreBoot0.
0080  */
0081 ENTRY(omap4_secondary_startup)
0082 hold:   ldr r12,=0x103
0083     dsb
0084     smc #0          @ read from AuxCoreBoot0
0085     mov r0, r0, lsr #9
0086     mrc p15, 0, r4, c0, c0, 5
0087     and r4, r4, #0x0f
0088     cmp r0, r4
0089     bne hold
0090
0091     /*
0092      * we've been released from the wait loop,secondary_stack
0093      * should now contain the SVC stack for this core
0094      */
0095     b   omap_secondary_startup
0096 ENDPROC(omap4_secondary_startup)
0097
0098 ENTRY(omap4460_secondary_startup)
0099 hold_2: ldr r12,=0x103
0100     dsb
0101     smc #0          @ read from AuxCoreBoot0
0102     mov r0, r0, lsr #9
0103     mrc p15, 0, r4, c0, c0, 5
0104     and r4, r4, #0x0f
0105     cmp r0, r4
0106     bne hold_2
0107
0108     /*
0109      * GIC distributor control register has changed between
0110      * CortexA9 r1pX and r2pX. The Control Register secure
0111      * banked version is now composed of 2 bits:
0112      * bit 0 == Secure Enable
0113      * bit 1 == Non-Secure Enable
0114      * The Non-Secure banked register has not changed
0115      * Because the ROM Code is based on the r1pX GIC, the CPU1
0116      * GIC restoration will cause a problem to CPU0 Non-Secure SW.
0117      * The workaround must be:
0118      * 1) Before doing the CPU1 wakeup, CPU0 must disable
0119      * the GIC distributor
0120      * 2) CPU1 must re-enable the GIC distributor on
0121      * it's wakeup path.
0122      */
0123     ldr r1, =OMAP44XX_GIC_DIST_BASE
0124     ldr r0, [r1]
0125     orr r0, #1
0126     str r0, [r1]
0127
0128     /*
0129      * we've been released from the wait loop,secondary_stack
0130      * should now contain the SVC stack for this core
0131      */
0132     b   omap_secondary_startup
0133 ENDPROC(omap4460_secondary_startup)