arm/mach-omap2/iomap.h

0001 /*
0002  * IO mappings for OMAP2+
0003  *
0004  * IO definitions for TI OMAP processors and boards
0005  *
0006  * Copied from arch/arm/mach-sa1100/include/mach/io.h
0007  * Copyright (C) 1997-1999 Russell King
0008  *
0009  * Copyright (C) 2009-2012 Texas Instruments
0010  * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
0011  *
0012  * This program is free software; you can redistribute it and/or modify it
0013  * under the terms of the GNU General Public License as published by the
0014  * Free Software Foundation; either version 2 of the License, or (at your
0015  * option) any later version.
0016  *
0017  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
0018  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
0019  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
0020  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
0021  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0022  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
0023  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0024  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0025  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0026  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0027  *
0028  * You should have received a copy of the  GNU General Public License along
0029  * with this program; if not, write  to the Free Software Foundation, Inc.,
0030  * 675 Mass Ave, Cambridge, MA 02139, USA.
0031  */
0032
0033 #define OMAP2_L3_IO_OFFSET  0x90000000
0034 #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
0035
0036 #define OMAP2_L4_IO_OFFSET  0xb2000000
0037 #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
0038
0039 #define OMAP4_L3_IO_OFFSET  0xb4000000
0040 #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
0041
0042 #define AM33XX_L4_WK_IO_OFFSET  0xb5000000
0043 #define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
0044
0045 #define OMAP4_L3_PER_IO_OFFSET  0xb1100000
0046 #define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
0047
0048 #define OMAP2_EMU_IO_OFFSET     0xaa800000  /* Emulation */
0049 #define OMAP2_EMU_IO_ADDRESS(pa)    IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
0050
0051 /*
0052  * ----------------------------------------------------------------------------
0053  * Omap2 specific IO mapping
0054  * ----------------------------------------------------------------------------
0055  */
0056
0057 /* We map both L3 and L4 on OMAP2 */
0058 #define L3_24XX_PHYS    L3_24XX_BASE    /* 0x68000000 --> 0xf8000000*/
0059 #define L3_24XX_VIRT    (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
0060 #define L3_24XX_SIZE    SZ_1M       /* 44kB of 128MB used, want 1MB sect */
0061 #define L4_24XX_PHYS    L4_24XX_BASE    /* 0x48000000 --> 0xfa000000 */
0062 #define L4_24XX_VIRT    (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
0063 #define L4_24XX_SIZE    SZ_1M       /* 1MB of 128MB used, want 1MB sect */
0064
0065 #define L4_WK_243X_PHYS     L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
0066 #define L4_WK_243X_VIRT     (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
0067 #define L4_WK_243X_SIZE     SZ_1M
0068 #define OMAP243X_GPMC_PHYS  OMAP243X_GPMC_BASE
0069 #define OMAP243X_GPMC_VIRT  (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
0070                         /* 0x6e000000 --> 0xfe000000 */
0071 #define OMAP243X_GPMC_SIZE  SZ_1M
0072 #define OMAP243X_SDRC_PHYS  OMAP243X_SDRC_BASE
0073                         /* 0x6D000000 --> 0xfd000000 */
0074 #define OMAP243X_SDRC_VIRT  (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
0075 #define OMAP243X_SDRC_SIZE  SZ_1M
0076 #define OMAP243X_SMS_PHYS   OMAP243X_SMS_BASE
0077                         /* 0x6c000000 --> 0xfc000000 */
0078 #define OMAP243X_SMS_VIRT   (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
0079 #define OMAP243X_SMS_SIZE   SZ_1M
0080
0081 /* 2420 IVA */
0082 #define DSP_MEM_2420_PHYS   OMAP2420_DSP_MEM_BASE
0083                         /* 0x58000000 --> 0xfc100000 */
0084 #define DSP_MEM_2420_VIRT   0xfc100000
0085 #define DSP_MEM_2420_SIZE   0x28000
0086 #define DSP_IPI_2420_PHYS   OMAP2420_DSP_IPI_BASE
0087                         /* 0x59000000 --> 0xfc128000 */
0088 #define DSP_IPI_2420_VIRT   0xfc128000
0089 #define DSP_IPI_2420_SIZE   SZ_4K
0090 #define DSP_MMU_2420_PHYS   OMAP2420_DSP_MMU_BASE
0091                         /* 0x5a000000 --> 0xfc129000 */
0092 #define DSP_MMU_2420_VIRT   0xfc129000
0093 #define DSP_MMU_2420_SIZE   SZ_4K
0094
0095 /* 2430 IVA2.1 - currently unmapped */
0096
0097 /*
0098  * ----------------------------------------------------------------------------
0099  * Omap3 specific IO mapping
0100  * ----------------------------------------------------------------------------
0101  */
0102
0103 /* We map both L3 and L4 on OMAP3 */
0104 #define L3_34XX_PHYS        L3_34XX_BASE    /* 0x68000000 --> 0xf8000000 */
0105 #define L3_34XX_VIRT        (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
0106 #define L3_34XX_SIZE        SZ_1M   /* 44kB of 128MB used, want 1MB sect */
0107
0108 #define L4_34XX_PHYS        L4_34XX_BASE    /* 0x48000000 --> 0xfa000000 */
0109 #define L4_34XX_VIRT        (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
0110 #define L4_34XX_SIZE        SZ_4M   /* 1MB of 128MB used, want 1MB sect */
0111
0112 /*
0113  * ----------------------------------------------------------------------------
0114  * AM33XX specific IO mapping
0115  * ----------------------------------------------------------------------------
0116  */
0117 #define L4_WK_AM33XX_PHYS   L4_WK_AM33XX_BASE
0118 #define L4_WK_AM33XX_VIRT   (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
0119 #define L4_WK_AM33XX_SIZE   SZ_4M   /* 1MB of 128MB used, want 1MB sect */
0120
0121 /*
0122  * Need to look at the Size 4M for L4.
0123  * VPOM3430 was not working for Int controller
0124  */
0125
0126 #define L4_PER_34XX_PHYS    L4_PER_34XX_BASE
0127                         /* 0x49000000 --> 0xfb000000 */
0128 #define L4_PER_34XX_VIRT    (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
0129 #define L4_PER_34XX_SIZE    SZ_1M
0130
0131 #define L4_EMU_34XX_PHYS    L4_EMU_34XX_BASE
0132                         /* 0x54000000 --> 0xfe800000 */
0133 #define L4_EMU_34XX_VIRT    (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
0134 #define L4_EMU_34XX_SIZE    SZ_8M
0135
0136 #define OMAP34XX_GPMC_PHYS  OMAP34XX_GPMC_BASE
0137                         /* 0x6e000000 --> 0xfe000000 */
0138 #define OMAP34XX_GPMC_VIRT  (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
0139 #define OMAP34XX_GPMC_SIZE  SZ_1M
0140
0141 #define OMAP343X_SMS_PHYS   OMAP343X_SMS_BASE
0142                         /* 0x6c000000 --> 0xfc000000 */
0143 #define OMAP343X_SMS_VIRT   (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
0144 #define OMAP343X_SMS_SIZE   SZ_1M
0145
0146 #define OMAP343X_SDRC_PHYS  OMAP343X_SDRC_BASE
0147                         /* 0x6D000000 --> 0xfd000000 */
0148 #define OMAP343X_SDRC_VIRT  (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
0149 #define OMAP343X_SDRC_SIZE  SZ_1M
0150
0151 /* 3430 IVA - currently unmapped */
0152
0153 /*
0154  * ----------------------------------------------------------------------------
0155  * Omap4 specific IO mapping
0156  * ----------------------------------------------------------------------------
0157  */
0158
0159 /* We map both L3 and L4 on OMAP4 */
0160 #define L3_44XX_PHYS        L3_44XX_BASE    /* 0x44000000 --> 0xf8000000 */
0161 #define L3_44XX_VIRT        (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
0162 #define L3_44XX_SIZE        SZ_1M
0163
0164 #define L4_44XX_PHYS        L4_44XX_BASE    /* 0x4a000000 --> 0xfc000000 */
0165 #define L4_44XX_VIRT        (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
0166 #define L4_44XX_SIZE        SZ_4M
0167
0168 #define L4_PER_44XX_PHYS    L4_PER_44XX_BASE
0169                         /* 0x48000000 --> 0xfa000000 */
0170 #define L4_PER_44XX_VIRT    (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
0171 #define L4_PER_44XX_SIZE    SZ_4M
0172
0173 #define L4_ABE_44XX_PHYS    L4_ABE_44XX_BASE
0174                         /* 0x49000000 --> 0xfb000000 */
0175 #define L4_ABE_44XX_VIRT    (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
0176 #define L4_ABE_44XX_SIZE    SZ_1M
0177 /*
0178  * ----------------------------------------------------------------------------
0179  * Omap5 specific IO mapping
0180  * ----------------------------------------------------------------------------
0181  */
0182 #define L3_54XX_PHYS        L3_54XX_BASE    /* 0x44000000 --> 0xf8000000 */
0183 #define L3_54XX_VIRT        (L3_54XX_PHYS + OMAP4_L3_IO_OFFSET)
0184 #define L3_54XX_SIZE        SZ_1M
0185
0186 #define L4_54XX_PHYS        L4_54XX_BASE    /* 0x4a000000 --> 0xfc000000 */
0187 #define L4_54XX_VIRT        (L4_54XX_PHYS + OMAP2_L4_IO_OFFSET)
0188 #define L4_54XX_SIZE        SZ_4M
0189
0190 #define L4_WK_54XX_PHYS     L4_WK_54XX_BASE /* 0x4ae00000 --> 0xfce00000 */
0191 #define L4_WK_54XX_VIRT     (L4_WK_54XX_PHYS + OMAP2_L4_IO_OFFSET)
0192 #define L4_WK_54XX_SIZE     SZ_2M
0193
0194 #define L4_PER_54XX_PHYS    L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */
0195 #define L4_PER_54XX_VIRT    (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET)
0196 #define L4_PER_54XX_SIZE    SZ_4M
0197
0198 /*
0199  * ----------------------------------------------------------------------------
0200  * DRA7xx specific IO mapping
0201  * ----------------------------------------------------------------------------
0202  */
0203 /*
0204  * L3_MAIN_SN_DRA7XX_PHYS 0x44000000 --> 0xf8000000
0205  * The overall space is 24MiB (0x4400_0000<->0x457F_FFFF), but mapping
0206  * everything is just inefficient, since, there are too many address holes.
0207  */
0208 #define L3_MAIN_SN_DRA7XX_PHYS      L3_MAIN_SN_DRA7XX_BASE
0209 #define L3_MAIN_SN_DRA7XX_VIRT      (L3_MAIN_SN_DRA7XX_PHYS + OMAP4_L3_IO_OFFSET)
0210 #define L3_MAIN_SN_DRA7XX_SIZE      SZ_1M
0211
0212 /*
0213  * L4_PER1_DRA7XX_PHYS  (0x4800_000<>0x480D_2FFF) -> 0.82MiB (alloc 1MiB)
0214  *  (0x48000000<->0x48100000) <=> (0xFA000000<->0xFA100000)
0215  */
0216 #define L4_PER1_DRA7XX_PHYS     L4_PER1_DRA7XX_BASE
0217 #define L4_PER1_DRA7XX_VIRT     (L4_PER1_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
0218 #define L4_PER1_DRA7XX_SIZE     SZ_1M
0219
0220 /*
0221  * L4_CFG_MPU_DRA7XX_PHYS   (0x48210000<>0x482A_F2FF) -> 0.62MiB (alloc 1MiB)
0222  *  (0x48210000<->0x48310000) <=> (0xFA210000<->0xFA310000)
0223  * NOTE: This is a bit of an orphan memory map sitting isolated in TRM
0224  */
0225 #define L4_CFG_MPU_DRA7XX_PHYS      L4_CFG_MPU_DRA7XX_BASE
0226 #define L4_CFG_MPU_DRA7XX_VIRT      (L4_CFG_MPU_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
0227 #define L4_CFG_MPU_DRA7XX_SIZE      SZ_1M
0228
0229 /*
0230  * L4_PER2_DRA7XX_PHYS  (0x4840_0000<>0x4848_8FFF) -> .53MiB (alloc 1MiB)
0231  *  (0x48400000<->0x48500000) <=> (0xFA400000<->0xFA500000)
0232  */
0233 #define L4_PER2_DRA7XX_PHYS     L4_PER2_DRA7XX_BASE
0234 #define L4_PER2_DRA7XX_VIRT     (L4_PER2_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
0235 #define L4_PER2_DRA7XX_SIZE     SZ_1M
0236
0237 /*
0238  * L4_PER3_DRA7XX_PHYS  (0x4880_0000<>0x489E_0FFF) -> 1.87MiB (alloc 2MiB)
0239  *  (0x48800000<->0x48A00000) <=> (0xFA800000<->0xFAA00000)
0240  */
0241 #define L4_PER3_DRA7XX_PHYS     L4_PER3_DRA7XX_BASE
0242 #define L4_PER3_DRA7XX_VIRT     (L4_PER3_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
0243 #define L4_PER3_DRA7XX_SIZE     SZ_2M
0244
0245 /*
0246  * L4_CFG_DRA7XX_PHYS   (0x4A00_0000<>0x4A22_BFFF) ->2.17MiB (alloc 3MiB)?
0247  *  (0x4A000000<->0x4A300000) <=> (0xFC000000<->0xFC300000)
0248  */
0249 #define L4_CFG_DRA7XX_PHYS      L4_CFG_DRA7XX_BASE
0250 #define L4_CFG_DRA7XX_VIRT      (L4_CFG_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
0251 #define L4_CFG_DRA7XX_SIZE      (SZ_1M + SZ_2M)
0252
0253 /*
0254  * L4_WKUP_DRA7XX_PHYS  (0x4AE0_0000<>0x4AE3_EFFF) -> .24 mb (alloc 1MiB)?
0255  *  (0x4AE00000<->4AF00000) <=> (0xFCE00000<->0xFCF00000)
0256  */
0257 #define L4_WKUP_DRA7XX_PHYS     L4_WKUP_DRA7XX_BASE
0258 #define L4_WKUP_DRA7XX_VIRT     (L4_WKUP_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
0259 #define L4_WKUP_DRA7XX_SIZE     SZ_1M