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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * linux/arch/arm/mach-omap2/io.c
0004  *
0005  * OMAP2 I/O mapping code
0006  *
0007  * Copyright (C) 2005 Nokia Corporation
0008  * Copyright (C) 2007-2009 Texas Instruments
0009  *
0010  * Author:
0011  *  Juha Yrjola <juha.yrjola@nokia.com>
0012  *  Syed Khasim <x0khasim@ti.com>
0013  *
0014  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
0015  */
0016 #include <linux/module.h>
0017 #include <linux/kernel.h>
0018 #include <linux/init.h>
0019 #include <linux/io.h>
0020 #include <linux/clk.h>
0021 
0022 #include <asm/tlb.h>
0023 #include <asm/mach/map.h>
0024 
0025 #include <linux/omap-dma.h>
0026 
0027 #include "omap_hwmod.h"
0028 #include "soc.h"
0029 #include "iomap.h"
0030 #include "voltage.h"
0031 #include "powerdomain.h"
0032 #include "clockdomain.h"
0033 #include "common.h"
0034 #include "clock.h"
0035 #include "clock2xxx.h"
0036 #include "clock3xxx.h"
0037 #include "sdrc.h"
0038 #include "control.h"
0039 #include "serial.h"
0040 #include "sram.h"
0041 #include "cm2xxx.h"
0042 #include "cm3xxx.h"
0043 #include "cm33xx.h"
0044 #include "cm44xx.h"
0045 #include "prm.h"
0046 #include "cm.h"
0047 #include "prcm_mpu44xx.h"
0048 #include "prminst44xx.h"
0049 #include "prm2xxx.h"
0050 #include "prm3xxx.h"
0051 #include "prm33xx.h"
0052 #include "prm44xx.h"
0053 #include "opp2xxx.h"
0054 #include "omap-secure.h"
0055 
0056 /*
0057  * omap_clk_soc_init: points to a function that does the SoC-specific
0058  * clock initializations
0059  */
0060 static int (*omap_clk_soc_init)(void);
0061 
0062 /*
0063  * The machine specific code may provide the extra mapping besides the
0064  * default mapping provided here.
0065  */
0066 
0067 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
0068 static struct map_desc omap24xx_io_desc[] __initdata = {
0069     {
0070         .virtual    = L3_24XX_VIRT,
0071         .pfn        = __phys_to_pfn(L3_24XX_PHYS),
0072         .length     = L3_24XX_SIZE,
0073         .type       = MT_DEVICE
0074     },
0075     {
0076         .virtual    = L4_24XX_VIRT,
0077         .pfn        = __phys_to_pfn(L4_24XX_PHYS),
0078         .length     = L4_24XX_SIZE,
0079         .type       = MT_DEVICE
0080     },
0081 };
0082 
0083 #ifdef CONFIG_SOC_OMAP2420
0084 static struct map_desc omap242x_io_desc[] __initdata = {
0085     {
0086         .virtual    = DSP_MEM_2420_VIRT,
0087         .pfn        = __phys_to_pfn(DSP_MEM_2420_PHYS),
0088         .length     = DSP_MEM_2420_SIZE,
0089         .type       = MT_DEVICE
0090     },
0091     {
0092         .virtual    = DSP_IPI_2420_VIRT,
0093         .pfn        = __phys_to_pfn(DSP_IPI_2420_PHYS),
0094         .length     = DSP_IPI_2420_SIZE,
0095         .type       = MT_DEVICE
0096     },
0097     {
0098         .virtual    = DSP_MMU_2420_VIRT,
0099         .pfn        = __phys_to_pfn(DSP_MMU_2420_PHYS),
0100         .length     = DSP_MMU_2420_SIZE,
0101         .type       = MT_DEVICE
0102     },
0103 };
0104 
0105 #endif
0106 
0107 #ifdef CONFIG_SOC_OMAP2430
0108 static struct map_desc omap243x_io_desc[] __initdata = {
0109     {
0110         .virtual    = L4_WK_243X_VIRT,
0111         .pfn        = __phys_to_pfn(L4_WK_243X_PHYS),
0112         .length     = L4_WK_243X_SIZE,
0113         .type       = MT_DEVICE
0114     },
0115     {
0116         .virtual    = OMAP243X_GPMC_VIRT,
0117         .pfn        = __phys_to_pfn(OMAP243X_GPMC_PHYS),
0118         .length     = OMAP243X_GPMC_SIZE,
0119         .type       = MT_DEVICE
0120     },
0121     {
0122         .virtual    = OMAP243X_SDRC_VIRT,
0123         .pfn        = __phys_to_pfn(OMAP243X_SDRC_PHYS),
0124         .length     = OMAP243X_SDRC_SIZE,
0125         .type       = MT_DEVICE
0126     },
0127     {
0128         .virtual    = OMAP243X_SMS_VIRT,
0129         .pfn        = __phys_to_pfn(OMAP243X_SMS_PHYS),
0130         .length     = OMAP243X_SMS_SIZE,
0131         .type       = MT_DEVICE
0132     },
0133 };
0134 #endif
0135 #endif
0136 
0137 #ifdef  CONFIG_ARCH_OMAP3
0138 static struct map_desc omap34xx_io_desc[] __initdata = {
0139     {
0140         .virtual    = L3_34XX_VIRT,
0141         .pfn        = __phys_to_pfn(L3_34XX_PHYS),
0142         .length     = L3_34XX_SIZE,
0143         .type       = MT_DEVICE
0144     },
0145     {
0146         .virtual    = L4_34XX_VIRT,
0147         .pfn        = __phys_to_pfn(L4_34XX_PHYS),
0148         .length     = L4_34XX_SIZE,
0149         .type       = MT_DEVICE
0150     },
0151     {
0152         .virtual    = OMAP34XX_GPMC_VIRT,
0153         .pfn        = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
0154         .length     = OMAP34XX_GPMC_SIZE,
0155         .type       = MT_DEVICE
0156     },
0157     {
0158         .virtual    = OMAP343X_SMS_VIRT,
0159         .pfn        = __phys_to_pfn(OMAP343X_SMS_PHYS),
0160         .length     = OMAP343X_SMS_SIZE,
0161         .type       = MT_DEVICE
0162     },
0163     {
0164         .virtual    = OMAP343X_SDRC_VIRT,
0165         .pfn        = __phys_to_pfn(OMAP343X_SDRC_PHYS),
0166         .length     = OMAP343X_SDRC_SIZE,
0167         .type       = MT_DEVICE
0168     },
0169     {
0170         .virtual    = L4_PER_34XX_VIRT,
0171         .pfn        = __phys_to_pfn(L4_PER_34XX_PHYS),
0172         .length     = L4_PER_34XX_SIZE,
0173         .type       = MT_DEVICE
0174     },
0175     {
0176         .virtual    = L4_EMU_34XX_VIRT,
0177         .pfn        = __phys_to_pfn(L4_EMU_34XX_PHYS),
0178         .length     = L4_EMU_34XX_SIZE,
0179         .type       = MT_DEVICE
0180     },
0181 };
0182 #endif
0183 
0184 #ifdef CONFIG_SOC_TI81XX
0185 static struct map_desc omapti81xx_io_desc[] __initdata = {
0186     {
0187         .virtual    = L4_34XX_VIRT,
0188         .pfn        = __phys_to_pfn(L4_34XX_PHYS),
0189         .length     = L4_34XX_SIZE,
0190         .type       = MT_DEVICE
0191     }
0192 };
0193 #endif
0194 
0195 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
0196 static struct map_desc omapam33xx_io_desc[] __initdata = {
0197     {
0198         .virtual    = L4_34XX_VIRT,
0199         .pfn        = __phys_to_pfn(L4_34XX_PHYS),
0200         .length     = L4_34XX_SIZE,
0201         .type       = MT_DEVICE
0202     },
0203     {
0204         .virtual    = L4_WK_AM33XX_VIRT,
0205         .pfn        = __phys_to_pfn(L4_WK_AM33XX_PHYS),
0206         .length     = L4_WK_AM33XX_SIZE,
0207         .type       = MT_DEVICE
0208     }
0209 };
0210 #endif
0211 
0212 #ifdef  CONFIG_ARCH_OMAP4
0213 static struct map_desc omap44xx_io_desc[] __initdata = {
0214     {
0215         .virtual    = L3_44XX_VIRT,
0216         .pfn        = __phys_to_pfn(L3_44XX_PHYS),
0217         .length     = L3_44XX_SIZE,
0218         .type       = MT_DEVICE,
0219     },
0220     {
0221         .virtual    = L4_44XX_VIRT,
0222         .pfn        = __phys_to_pfn(L4_44XX_PHYS),
0223         .length     = L4_44XX_SIZE,
0224         .type       = MT_DEVICE,
0225     },
0226     {
0227         .virtual    = L4_PER_44XX_VIRT,
0228         .pfn        = __phys_to_pfn(L4_PER_44XX_PHYS),
0229         .length     = L4_PER_44XX_SIZE,
0230         .type       = MT_DEVICE,
0231     },
0232 };
0233 #endif
0234 
0235 #ifdef CONFIG_SOC_OMAP5
0236 static struct map_desc omap54xx_io_desc[] __initdata = {
0237     {
0238         .virtual    = L3_54XX_VIRT,
0239         .pfn        = __phys_to_pfn(L3_54XX_PHYS),
0240         .length     = L3_54XX_SIZE,
0241         .type       = MT_DEVICE,
0242     },
0243     {
0244         .virtual    = L4_54XX_VIRT,
0245         .pfn        = __phys_to_pfn(L4_54XX_PHYS),
0246         .length     = L4_54XX_SIZE,
0247         .type       = MT_DEVICE,
0248     },
0249     {
0250         .virtual    = L4_WK_54XX_VIRT,
0251         .pfn        = __phys_to_pfn(L4_WK_54XX_PHYS),
0252         .length     = L4_WK_54XX_SIZE,
0253         .type       = MT_DEVICE,
0254     },
0255     {
0256         .virtual    = L4_PER_54XX_VIRT,
0257         .pfn        = __phys_to_pfn(L4_PER_54XX_PHYS),
0258         .length     = L4_PER_54XX_SIZE,
0259         .type       = MT_DEVICE,
0260     },
0261 };
0262 #endif
0263 
0264 #ifdef CONFIG_SOC_DRA7XX
0265 static struct map_desc dra7xx_io_desc[] __initdata = {
0266     {
0267         .virtual    = L4_CFG_MPU_DRA7XX_VIRT,
0268         .pfn        = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
0269         .length     = L4_CFG_MPU_DRA7XX_SIZE,
0270         .type       = MT_DEVICE,
0271     },
0272     {
0273         .virtual    = L3_MAIN_SN_DRA7XX_VIRT,
0274         .pfn        = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
0275         .length     = L3_MAIN_SN_DRA7XX_SIZE,
0276         .type       = MT_DEVICE,
0277     },
0278     {
0279         .virtual    = L4_PER1_DRA7XX_VIRT,
0280         .pfn        = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
0281         .length     = L4_PER1_DRA7XX_SIZE,
0282         .type       = MT_DEVICE,
0283     },
0284     {
0285         .virtual    = L4_PER2_DRA7XX_VIRT,
0286         .pfn        = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
0287         .length     = L4_PER2_DRA7XX_SIZE,
0288         .type       = MT_DEVICE,
0289     },
0290     {
0291         .virtual    = L4_PER3_DRA7XX_VIRT,
0292         .pfn        = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
0293         .length     = L4_PER3_DRA7XX_SIZE,
0294         .type       = MT_DEVICE,
0295     },
0296     {
0297         .virtual    = L4_CFG_DRA7XX_VIRT,
0298         .pfn        = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
0299         .length     = L4_CFG_DRA7XX_SIZE,
0300         .type       = MT_DEVICE,
0301     },
0302     {
0303         .virtual    = L4_WKUP_DRA7XX_VIRT,
0304         .pfn        = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
0305         .length     = L4_WKUP_DRA7XX_SIZE,
0306         .type       = MT_DEVICE,
0307     },
0308 };
0309 #endif
0310 
0311 #ifdef CONFIG_SOC_OMAP2420
0312 void __init omap242x_map_io(void)
0313 {
0314     iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
0315     iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
0316 }
0317 #endif
0318 
0319 #ifdef CONFIG_SOC_OMAP2430
0320 void __init omap243x_map_io(void)
0321 {
0322     iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
0323     iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
0324 }
0325 #endif
0326 
0327 #ifdef CONFIG_ARCH_OMAP3
0328 void __init omap3_map_io(void)
0329 {
0330     iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
0331 }
0332 #endif
0333 
0334 #ifdef CONFIG_SOC_TI81XX
0335 void __init ti81xx_map_io(void)
0336 {
0337     iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
0338 }
0339 #endif
0340 
0341 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
0342 void __init am33xx_map_io(void)
0343 {
0344     iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
0345 }
0346 #endif
0347 
0348 #ifdef CONFIG_ARCH_OMAP4
0349 void __init omap4_map_io(void)
0350 {
0351     iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
0352     omap_barriers_init();
0353 }
0354 #endif
0355 
0356 #ifdef CONFIG_SOC_OMAP5
0357 void __init omap5_map_io(void)
0358 {
0359     iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
0360     omap_barriers_init();
0361 }
0362 #endif
0363 
0364 #ifdef CONFIG_SOC_DRA7XX
0365 void __init dra7xx_map_io(void)
0366 {
0367     iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
0368     omap_barriers_init();
0369 }
0370 #endif
0371 /*
0372  * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
0373  *
0374  * Sets the CORE DPLL3 M2 divider to the same value that it's at
0375  * currently.  This has the effect of setting the SDRC SDRAM AC timing
0376  * registers to the values currently defined by the kernel.  Currently
0377  * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
0378  * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
0379  * or passes along the return value of clk_set_rate().
0380  */
0381 static int __init _omap2_init_reprogram_sdrc(void)
0382 {
0383     struct clk *dpll3_m2_ck;
0384     int v = -EINVAL;
0385     long rate;
0386 
0387     if (!cpu_is_omap34xx())
0388         return 0;
0389 
0390     dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
0391     if (IS_ERR(dpll3_m2_ck))
0392         return -EINVAL;
0393 
0394     rate = clk_get_rate(dpll3_m2_ck);
0395     pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
0396     v = clk_set_rate(dpll3_m2_ck, rate);
0397     if (v)
0398         pr_err("dpll3_m2_clk rate change failed: %d\n", v);
0399 
0400     clk_put(dpll3_m2_ck);
0401 
0402     return v;
0403 }
0404 
0405 #ifdef CONFIG_OMAP_HWMOD
0406 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
0407 {
0408     return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
0409 }
0410 
0411 static void __init __maybe_unused omap_hwmod_init_postsetup(void)
0412 {
0413     u8 postsetup_state = _HWMOD_STATE_DEFAULT;
0414 
0415     /* Set the default postsetup state for all hwmods */
0416     omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
0417 }
0418 #else
0419 static inline void omap_hwmod_init_postsetup(void)
0420 {
0421 }
0422 #endif
0423 
0424 #ifdef CONFIG_SOC_OMAP2420
0425 void __init omap2420_init_early(void)
0426 {
0427     omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
0428     omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
0429                    OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
0430     omap2_control_base_init();
0431     omap2xxx_check_revision();
0432     omap2_prcm_base_init();
0433     omap2xxx_voltagedomains_init();
0434     omap242x_powerdomains_init();
0435     omap242x_clockdomains_init();
0436     omap2420_hwmod_init();
0437     omap_hwmod_init_postsetup();
0438     omap_clk_soc_init = omap2420_dt_clk_init;
0439     rate_table = omap2420_rate_table;
0440 }
0441 
0442 void __init omap2420_init_late(void)
0443 {
0444     omap_pm_soc_init = omap2_pm_init;
0445 }
0446 #endif
0447 
0448 #ifdef CONFIG_SOC_OMAP2430
0449 void __init omap2430_init_early(void)
0450 {
0451     omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
0452     omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
0453                    OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
0454     omap2_control_base_init();
0455     omap2xxx_check_revision();
0456     omap2_prcm_base_init();
0457     omap2xxx_voltagedomains_init();
0458     omap243x_powerdomains_init();
0459     omap243x_clockdomains_init();
0460     omap2430_hwmod_init();
0461     omap_hwmod_init_postsetup();
0462     omap_clk_soc_init = omap2430_dt_clk_init;
0463     rate_table = omap2430_rate_table;
0464 }
0465 
0466 void __init omap2430_init_late(void)
0467 {
0468     omap_pm_soc_init = omap2_pm_init;
0469 }
0470 #endif
0471 
0472 /*
0473  * Currently only board-omap3beagle.c should call this because of the
0474  * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
0475  */
0476 #ifdef CONFIG_ARCH_OMAP3
0477 void __init omap3_init_early(void)
0478 {
0479     omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
0480     omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
0481                    OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
0482     omap2_control_base_init();
0483     omap3xxx_check_revision();
0484     omap3xxx_check_features();
0485     omap2_prcm_base_init();
0486     omap3xxx_voltagedomains_init();
0487     omap3xxx_powerdomains_init();
0488     omap3xxx_clockdomains_init();
0489     omap3xxx_hwmod_init();
0490     omap_hwmod_init_postsetup();
0491     omap_secure_init();
0492 }
0493 
0494 void __init omap3430_init_early(void)
0495 {
0496     omap3_init_early();
0497     omap_clk_soc_init = omap3430_dt_clk_init;
0498 }
0499 
0500 void __init omap35xx_init_early(void)
0501 {
0502     omap3_init_early();
0503     omap_clk_soc_init = omap3430_dt_clk_init;
0504 }
0505 
0506 void __init omap3630_init_early(void)
0507 {
0508     omap3_init_early();
0509     omap_clk_soc_init = omap3630_dt_clk_init;
0510 }
0511 
0512 void __init am35xx_init_early(void)
0513 {
0514     omap3_init_early();
0515     omap_clk_soc_init = am35xx_dt_clk_init;
0516 }
0517 
0518 void __init omap3_init_late(void)
0519 {
0520     omap_pm_soc_init = omap3_pm_init;
0521 }
0522 
0523 void __init ti81xx_init_late(void)
0524 {
0525     omap_pm_soc_init = omap_pm_nop_init;
0526 }
0527 #endif
0528 
0529 #ifdef CONFIG_SOC_TI81XX
0530 void __init ti814x_init_early(void)
0531 {
0532     omap2_set_globals_tap(TI814X_CLASS,
0533                   OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
0534     omap2_control_base_init();
0535     omap3xxx_check_revision();
0536     ti81xx_check_features();
0537     omap2_prcm_base_init();
0538     omap3xxx_voltagedomains_init();
0539     omap3xxx_powerdomains_init();
0540     ti814x_clockdomains_init();
0541     dm814x_hwmod_init();
0542     omap_hwmod_init_postsetup();
0543     omap_clk_soc_init = dm814x_dt_clk_init;
0544     omap_secure_init();
0545 }
0546 
0547 void __init ti816x_init_early(void)
0548 {
0549     omap2_set_globals_tap(TI816X_CLASS,
0550                   OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
0551     omap2_control_base_init();
0552     omap3xxx_check_revision();
0553     ti81xx_check_features();
0554     omap2_prcm_base_init();
0555     omap3xxx_voltagedomains_init();
0556     omap3xxx_powerdomains_init();
0557     ti816x_clockdomains_init();
0558     dm816x_hwmod_init();
0559     omap_hwmod_init_postsetup();
0560     omap_clk_soc_init = dm816x_dt_clk_init;
0561     omap_secure_init();
0562 }
0563 #endif
0564 
0565 #ifdef CONFIG_SOC_AM33XX
0566 void __init am33xx_init_early(void)
0567 {
0568     omap2_set_globals_tap(AM335X_CLASS,
0569                   AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
0570     omap2_control_base_init();
0571     omap3xxx_check_revision();
0572     am33xx_check_features();
0573     omap2_prcm_base_init();
0574     am33xx_powerdomains_init();
0575     am33xx_clockdomains_init();
0576     omap_clk_soc_init = am33xx_dt_clk_init;
0577     omap_secure_init();
0578 }
0579 
0580 void __init am33xx_init_late(void)
0581 {
0582     omap_pm_soc_init = amx3_common_pm_init;
0583 }
0584 #endif
0585 
0586 #ifdef CONFIG_SOC_AM43XX
0587 void __init am43xx_init_early(void)
0588 {
0589     omap2_set_globals_tap(AM335X_CLASS,
0590                   AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
0591     omap2_control_base_init();
0592     omap3xxx_check_revision();
0593     am33xx_check_features();
0594     omap2_prcm_base_init();
0595     am43xx_powerdomains_init();
0596     am43xx_clockdomains_init();
0597     omap_l2_cache_init();
0598     omap_clk_soc_init = am43xx_dt_clk_init;
0599     omap_secure_init();
0600 }
0601 
0602 void __init am43xx_init_late(void)
0603 {
0604     omap_pm_soc_init = amx3_common_pm_init;
0605 }
0606 #endif
0607 
0608 #ifdef CONFIG_ARCH_OMAP4
0609 void __init omap4430_init_early(void)
0610 {
0611     omap2_set_globals_tap(OMAP443X_CLASS,
0612                   OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
0613     omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
0614     omap2_control_base_init();
0615     omap4xxx_check_revision();
0616     omap4xxx_check_features();
0617     omap2_prcm_base_init();
0618     omap4_sar_ram_init();
0619     omap4_mpuss_early_init();
0620     omap4_pm_init_early();
0621     omap44xx_voltagedomains_init();
0622     omap44xx_powerdomains_init();
0623     omap44xx_clockdomains_init();
0624     omap_l2_cache_init();
0625     omap_clk_soc_init = omap4xxx_dt_clk_init;
0626     omap_secure_init();
0627 }
0628 
0629 void __init omap4430_init_late(void)
0630 {
0631     omap_pm_soc_init = omap4_pm_init;
0632 }
0633 #endif
0634 
0635 #ifdef CONFIG_SOC_OMAP5
0636 void __init omap5_init_early(void)
0637 {
0638     omap2_set_globals_tap(OMAP54XX_CLASS,
0639                   OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
0640     omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
0641     omap2_control_base_init();
0642     omap2_prcm_base_init();
0643     omap5xxx_check_revision();
0644     omap4_sar_ram_init();
0645     omap4_mpuss_early_init();
0646     omap4_pm_init_early();
0647     omap54xx_voltagedomains_init();
0648     omap54xx_powerdomains_init();
0649     omap54xx_clockdomains_init();
0650     omap_clk_soc_init = omap5xxx_dt_clk_init;
0651     omap_secure_init();
0652 }
0653 
0654 void __init omap5_init_late(void)
0655 {
0656     omap_pm_soc_init = omap4_pm_init;
0657 }
0658 #endif
0659 
0660 #ifdef CONFIG_SOC_DRA7XX
0661 void __init dra7xx_init_early(void)
0662 {
0663     omap2_set_globals_tap(DRA7XX_CLASS,
0664                   OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
0665     omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
0666     omap2_control_base_init();
0667     omap4_pm_init_early();
0668     omap2_prcm_base_init();
0669     dra7xxx_check_revision();
0670     dra7xx_powerdomains_init();
0671     dra7xx_clockdomains_init();
0672     omap_clk_soc_init = dra7xx_dt_clk_init;
0673     omap_secure_init();
0674 }
0675 
0676 void __init dra7xx_init_late(void)
0677 {
0678     omap_pm_soc_init = omap4_pm_init;
0679 }
0680 #endif
0681 
0682 
0683 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
0684                       struct omap_sdrc_params *sdrc_cs1)
0685 {
0686     omap_sram_init();
0687 
0688     if (cpu_is_omap24xx() || omap3_has_sdrc()) {
0689         omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
0690         _omap2_init_reprogram_sdrc();
0691     }
0692 }
0693 
0694 int __init omap_clk_init(void)
0695 {
0696     int ret = 0;
0697 
0698     if (!omap_clk_soc_init)
0699         return 0;
0700 
0701     ti_clk_init_features();
0702 
0703     omap2_clk_setup_ll_ops();
0704 
0705     ret = omap_control_init();
0706     if (ret)
0707         return ret;
0708 
0709     ret = omap_prcm_init();
0710     if (ret)
0711         return ret;
0712 
0713     of_clk_init(NULL);
0714 
0715     ti_dt_clk_init_retry_clks();
0716 
0717     ti_dt_clockdomains_setup();
0718 
0719     ret = omap_clk_soc_init();
0720 
0721     return ret;
0722 }
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