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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * linux/arch/arm/mach-omap2/id.c
0004  *
0005  * OMAP2 CPU identification code
0006  *
0007  * Copyright (C) 2005 Nokia Corporation
0008  * Written by Tony Lindgren <tony@atomide.com>
0009  *
0010  * Copyright (C) 2009-11 Texas Instruments
0011  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
0012  */
0013 
0014 #include <linux/module.h>
0015 #include <linux/kernel.h>
0016 #include <linux/init.h>
0017 #include <linux/io.h>
0018 #include <linux/random.h>
0019 #include <linux/slab.h>
0020 
0021 #ifdef CONFIG_SOC_BUS
0022 #include <linux/sys_soc.h>
0023 #endif
0024 
0025 #include <asm/cputype.h>
0026 
0027 #include "common.h"
0028 
0029 #include "id.h"
0030 
0031 #include "soc.h"
0032 #include "control.h"
0033 
0034 #define OMAP4_SILICON_TYPE_STANDARD     0x01
0035 #define OMAP4_SILICON_TYPE_PERFORMANCE      0x02
0036 
0037 #define OMAP_SOC_MAX_NAME_LENGTH        16
0038 
0039 static unsigned int omap_revision;
0040 static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
0041 static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
0042 u32 omap_features;
0043 
0044 unsigned int omap_rev(void)
0045 {
0046     return omap_revision;
0047 }
0048 EXPORT_SYMBOL(omap_rev);
0049 
0050 int omap_type(void)
0051 {
0052     static u32 val = OMAP2_DEVICETYPE_MASK;
0053 
0054     if (val < OMAP2_DEVICETYPE_MASK)
0055         return val;
0056 
0057     if (soc_is_omap24xx()) {
0058         val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
0059     } else if (soc_is_ti81xx()) {
0060         val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
0061     } else if (soc_is_am33xx() || soc_is_am43xx()) {
0062         val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
0063     } else if (soc_is_omap34xx()) {
0064         val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
0065     } else if (soc_is_omap44xx()) {
0066         val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
0067     } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
0068         val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
0069         val &= OMAP5_DEVICETYPE_MASK;
0070         val >>= 6;
0071         goto out;
0072     } else {
0073         pr_err("Cannot detect omap type!\n");
0074         goto out;
0075     }
0076 
0077     val &= OMAP2_DEVICETYPE_MASK;
0078     val >>= 8;
0079 
0080 out:
0081     return val;
0082 }
0083 EXPORT_SYMBOL(omap_type);
0084 
0085 
0086 /*----------------------------------------------------------------------------*/
0087 
0088 #define OMAP_TAP_IDCODE     0x0204
0089 #define OMAP_TAP_DIE_ID_0   0x0218
0090 #define OMAP_TAP_DIE_ID_1   0x021C
0091 #define OMAP_TAP_DIE_ID_2   0x0220
0092 #define OMAP_TAP_DIE_ID_3   0x0224
0093 
0094 #define OMAP_TAP_DIE_ID_44XX_0  0x0200
0095 #define OMAP_TAP_DIE_ID_44XX_1  0x0208
0096 #define OMAP_TAP_DIE_ID_44XX_2  0x020c
0097 #define OMAP_TAP_DIE_ID_44XX_3  0x0210
0098 
0099 #define read_tap_reg(reg)   readl_relaxed(tap_base  + (reg))
0100 
0101 struct omap_id {
0102     u16 hawkeye;    /* Silicon type (Hawkeye id) */
0103     u8  dev;        /* Device type from production_id reg */
0104     u32 type;       /* Combined type id copied to omap_revision */
0105 };
0106 
0107 /* Register values to detect the OMAP version */
0108 static struct omap_id omap_ids[] __initdata = {
0109     { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
0110     { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
0111     { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
0112     { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
0113     { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
0114     { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
0115 };
0116 
0117 static void __iomem *tap_base;
0118 static u16 tap_prod_id;
0119 
0120 void omap_get_die_id(struct omap_die_id *odi)
0121 {
0122     if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
0123         odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
0124         odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
0125         odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
0126         odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
0127 
0128         return;
0129     }
0130     odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
0131     odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
0132     odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
0133     odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
0134 }
0135 
0136 static int __init omap_feed_randpool(void)
0137 {
0138     struct omap_die_id odi;
0139 
0140     /* Throw the die ID into the entropy pool at boot */
0141     omap_get_die_id(&odi);
0142     add_device_randomness(&odi, sizeof(odi));
0143     return 0;
0144 }
0145 omap_device_initcall(omap_feed_randpool);
0146 
0147 void __init omap2xxx_check_revision(void)
0148 {
0149     int i, j;
0150     u32 idcode, prod_id;
0151     u16 hawkeye;
0152     u8  dev_type, rev;
0153     struct omap_die_id odi;
0154 
0155     idcode = read_tap_reg(OMAP_TAP_IDCODE);
0156     prod_id = read_tap_reg(tap_prod_id);
0157     hawkeye = (idcode >> 12) & 0xffff;
0158     rev = (idcode >> 28) & 0x0f;
0159     dev_type = (prod_id >> 16) & 0x0f;
0160     omap_get_die_id(&odi);
0161 
0162     pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
0163          idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
0164     pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
0165     pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
0166          odi.id_1, (odi.id_1 >> 28) & 0xf);
0167     pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
0168     pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
0169     pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
0170          prod_id, dev_type);
0171 
0172     /* Check hawkeye ids */
0173     for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
0174         if (hawkeye == omap_ids[i].hawkeye)
0175             break;
0176     }
0177 
0178     if (i == ARRAY_SIZE(omap_ids)) {
0179         printk(KERN_ERR "Unknown OMAP CPU id\n");
0180         return;
0181     }
0182 
0183     for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
0184         if (dev_type == omap_ids[j].dev)
0185             break;
0186     }
0187 
0188     if (j == ARRAY_SIZE(omap_ids)) {
0189         pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
0190                omap_ids[i].type >> 16);
0191         j = i;
0192     }
0193 
0194     sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
0195     sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
0196 
0197     pr_info("%s", soc_name);
0198     if ((omap_rev() >> 8) & 0x0f)
0199         pr_cont("%s", soc_rev);
0200     pr_cont("\n");
0201 }
0202 
0203 #define OMAP3_SHOW_FEATURE(feat)        \
0204     if (omap3_has_ ##feat())        \
0205         n += scnprintf(buf + n, sizeof(buf) - n, #feat " ");
0206 
0207 static void __init omap3_cpuinfo(void)
0208 {
0209     const char *cpu_name;
0210     char buf[64];
0211     int n = 0;
0212 
0213     memset(buf, 0, sizeof(buf));
0214 
0215     /*
0216      * OMAP3430 and OMAP3530 are assumed to be same.
0217      *
0218      * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
0219      * on available features. Upon detection, update the CPU id
0220      * and CPU class bits.
0221      */
0222     if (soc_is_omap3630()) {
0223         if (omap3_has_iva() && omap3_has_sgx()) {
0224             cpu_name = (omap3_has_isp()) ? "OMAP3630/DM3730" : "OMAP3621";
0225         } else if (omap3_has_iva()) {
0226             cpu_name = "DM3725";
0227         } else if (omap3_has_sgx()) {
0228             cpu_name = "OMAP3615/AM3715";
0229         } else {
0230             cpu_name = (omap3_has_isp()) ? "AM3703" : "OMAP3611";
0231         }
0232     } else if (soc_is_am35xx()) {
0233         cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
0234     } else if (soc_is_ti816x()) {
0235         cpu_name = "TI816X";
0236     } else if (soc_is_am335x()) {
0237         cpu_name =  "AM335X";
0238     } else if (soc_is_am437x()) {
0239         cpu_name =  "AM437x";
0240     } else if (soc_is_ti814x()) {
0241         cpu_name = "TI814X";
0242     } else if (omap3_has_iva() && omap3_has_sgx()) {
0243         /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
0244         cpu_name = "OMAP3430/3530";
0245     } else if (omap3_has_iva()) {
0246         cpu_name = "OMAP3525";
0247     } else if (omap3_has_sgx()) {
0248         cpu_name = "OMAP3515";
0249     } else {
0250         cpu_name = "OMAP3503";
0251     }
0252 
0253     scnprintf(soc_name, sizeof(soc_name), "%s", cpu_name);
0254 
0255     /* Print verbose information */
0256     n += scnprintf(buf, sizeof(buf) - n, "%s %s (", soc_name, soc_rev);
0257 
0258     OMAP3_SHOW_FEATURE(l2cache);
0259     OMAP3_SHOW_FEATURE(iva);
0260     OMAP3_SHOW_FEATURE(sgx);
0261     OMAP3_SHOW_FEATURE(neon);
0262     OMAP3_SHOW_FEATURE(isp);
0263     OMAP3_SHOW_FEATURE(192mhz_clk);
0264     if (*(buf + n - 1) == ' ')
0265         n--;
0266     n += scnprintf(buf + n, sizeof(buf) - n, ")\n");
0267     pr_info("%s", buf);
0268 }
0269 
0270 #define OMAP3_CHECK_FEATURE(status,feat)                \
0271     if (((status & OMAP3_ ##feat## _MASK)               \
0272         >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) {   \
0273         omap_features |= OMAP3_HAS_ ##feat;         \
0274     }
0275 
0276 void __init omap3xxx_check_features(void)
0277 {
0278     u32 status;
0279 
0280     omap_features = 0;
0281 
0282     status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
0283 
0284     OMAP3_CHECK_FEATURE(status, L2CACHE);
0285     OMAP3_CHECK_FEATURE(status, IVA);
0286     OMAP3_CHECK_FEATURE(status, SGX);
0287     OMAP3_CHECK_FEATURE(status, NEON);
0288     OMAP3_CHECK_FEATURE(status, ISP);
0289     if (soc_is_omap3630())
0290         omap_features |= OMAP3_HAS_192MHZ_CLK;
0291     if (soc_is_omap3430() || soc_is_omap3630())
0292         omap_features |= OMAP3_HAS_IO_WAKEUP;
0293     if (soc_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
0294         omap_rev() == OMAP3430_REV_ES3_1_2)
0295         omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
0296 
0297     omap_features |= OMAP3_HAS_SDRC;
0298 
0299     /*
0300      * am35x fixups:
0301      * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
0302      *   reserved and therefore return 0 when read.  Unfortunately,
0303      *   OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
0304      *   mean that a feature is present even though it isn't so clear
0305      *   the incorrectly set feature bits.
0306      */
0307     if (soc_is_am35xx())
0308         omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
0309 
0310     /*
0311      * TODO: Get additional info (where applicable)
0312      *       e.g. Size of L2 cache.
0313      */
0314 
0315     omap3_cpuinfo();
0316 }
0317 
0318 void __init omap4xxx_check_features(void)
0319 {
0320     u32 si_type;
0321 
0322     si_type =
0323     (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
0324 
0325     if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
0326         omap_features = OMAP4_HAS_PERF_SILICON;
0327 }
0328 
0329 void __init ti81xx_check_features(void)
0330 {
0331     omap_features = OMAP3_HAS_NEON;
0332     omap3_cpuinfo();
0333 }
0334 
0335 void __init am33xx_check_features(void)
0336 {
0337     u32 status;
0338 
0339     omap_features = OMAP3_HAS_NEON;
0340 
0341     status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
0342     if (status & AM33XX_SGX_MASK)
0343         omap_features |= OMAP3_HAS_SGX;
0344 
0345     omap3_cpuinfo();
0346 }
0347 
0348 void __init omap3xxx_check_revision(void)
0349 {
0350     const char *cpu_rev;
0351     u32 cpuid, idcode;
0352     u16 hawkeye;
0353     u8 rev;
0354 
0355     /*
0356      * We cannot access revision registers on ES1.0.
0357      * If the processor type is Cortex-A8 and the revision is 0x0
0358      * it means its Cortex r0p0 which is 3430 ES1.0.
0359      */
0360     cpuid = read_cpuid_id();
0361     if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
0362         omap_revision = OMAP3430_REV_ES1_0;
0363         cpu_rev = "1.0";
0364         return;
0365     }
0366 
0367     /*
0368      * Detection for 34xx ES2.0 and above can be done with just
0369      * hawkeye and rev. See TRM 1.5.2 Device Identification.
0370      * Note that rev does not map directly to our defined processor
0371      * revision numbers as ES1.0 uses value 0.
0372      */
0373     idcode = read_tap_reg(OMAP_TAP_IDCODE);
0374     hawkeye = (idcode >> 12) & 0xffff;
0375     rev = (idcode >> 28) & 0xff;
0376 
0377     switch (hawkeye) {
0378     case 0xb7ae:
0379         /* Handle 34xx/35xx devices */
0380         switch (rev) {
0381         case 0: /* Take care of early samples */
0382         case 1:
0383             omap_revision = OMAP3430_REV_ES2_0;
0384             cpu_rev = "2.0";
0385             break;
0386         case 2:
0387             omap_revision = OMAP3430_REV_ES2_1;
0388             cpu_rev = "2.1";
0389             break;
0390         case 3:
0391             omap_revision = OMAP3430_REV_ES3_0;
0392             cpu_rev = "3.0";
0393             break;
0394         case 4:
0395             omap_revision = OMAP3430_REV_ES3_1;
0396             cpu_rev = "3.1";
0397             break;
0398         case 7:
0399         default:
0400             /* Use the latest known revision as default */
0401             omap_revision = OMAP3430_REV_ES3_1_2;
0402             cpu_rev = "3.1.2";
0403         }
0404         break;
0405     case 0xb868:
0406         /*
0407          * Handle OMAP/AM 3505/3517 devices
0408          *
0409          * Set the device to be OMAP3517 here. Actual device
0410          * is identified later based on the features.
0411          */
0412         switch (rev) {
0413         case 0:
0414             omap_revision = AM35XX_REV_ES1_0;
0415             cpu_rev = "1.0";
0416             break;
0417         case 1:
0418         default:
0419             omap_revision = AM35XX_REV_ES1_1;
0420             cpu_rev = "1.1";
0421         }
0422         break;
0423     case 0xb891:
0424         /* Handle 36xx devices */
0425 
0426         switch(rev) {
0427         case 0: /* Take care of early samples */
0428             omap_revision = OMAP3630_REV_ES1_0;
0429             cpu_rev = "1.0";
0430             break;
0431         case 1:
0432             omap_revision = OMAP3630_REV_ES1_1;
0433             cpu_rev = "1.1";
0434             break;
0435         case 2:
0436         default:
0437             omap_revision = OMAP3630_REV_ES1_2;
0438             cpu_rev = "1.2";
0439         }
0440         break;
0441     case 0xb81e:
0442         switch (rev) {
0443         case 0:
0444             omap_revision = TI8168_REV_ES1_0;
0445             cpu_rev = "1.0";
0446             break;
0447         case 1:
0448             omap_revision = TI8168_REV_ES1_1;
0449             cpu_rev = "1.1";
0450             break;
0451         case 2:
0452             omap_revision = TI8168_REV_ES2_0;
0453             cpu_rev = "2.0";
0454             break;
0455         case 3:
0456         default:
0457             omap_revision = TI8168_REV_ES2_1;
0458             cpu_rev = "2.1";
0459         }
0460         break;
0461     case 0xb944:
0462         switch (rev) {
0463         case 0:
0464             omap_revision = AM335X_REV_ES1_0;
0465             cpu_rev = "1.0";
0466             break;
0467         case 1:
0468             omap_revision = AM335X_REV_ES2_0;
0469             cpu_rev = "2.0";
0470             break;
0471         case 2:
0472         default:
0473             omap_revision = AM335X_REV_ES2_1;
0474             cpu_rev = "2.1";
0475             break;
0476         }
0477         break;
0478     case 0xb98c:
0479         switch (rev) {
0480         case 0:
0481             omap_revision = AM437X_REV_ES1_0;
0482             cpu_rev = "1.0";
0483             break;
0484         case 1:
0485             omap_revision = AM437X_REV_ES1_1;
0486             cpu_rev = "1.1";
0487             break;
0488         case 2:
0489         default:
0490             omap_revision = AM437X_REV_ES1_2;
0491             cpu_rev = "1.2";
0492             break;
0493         }
0494         break;
0495     case 0xb8f2:
0496     case 0xb968:
0497         switch (rev) {
0498         case 0:
0499         case 1:
0500             omap_revision = TI8148_REV_ES1_0;
0501             cpu_rev = "1.0";
0502             break;
0503         case 2:
0504             omap_revision = TI8148_REV_ES2_0;
0505             cpu_rev = "2.0";
0506             break;
0507         case 3:
0508         default:
0509             omap_revision = TI8148_REV_ES2_1;
0510             cpu_rev = "2.1";
0511             break;
0512         }
0513         break;
0514     default:
0515         /* Unknown default to latest silicon rev as default */
0516         omap_revision = OMAP3630_REV_ES1_2;
0517         cpu_rev = "1.2";
0518         pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n",
0519             hawkeye);
0520     }
0521     sprintf(soc_rev, "ES%s", cpu_rev);
0522 }
0523 
0524 void __init omap4xxx_check_revision(void)
0525 {
0526     u32 idcode;
0527     u16 hawkeye;
0528     u8 rev;
0529 
0530     /*
0531      * The IC rev detection is done with hawkeye and rev.
0532      * Note that rev does not map directly to defined processor
0533      * revision numbers as ES1.0 uses value 0.
0534      */
0535     idcode = read_tap_reg(OMAP_TAP_IDCODE);
0536     hawkeye = (idcode >> 12) & 0xffff;
0537     rev = (idcode >> 28) & 0xf;
0538 
0539     /*
0540      * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
0541      * Use ARM register to detect the correct ES version
0542      */
0543     if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
0544         idcode = read_cpuid_id();
0545         rev = (idcode & 0xf) - 1;
0546     }
0547 
0548     switch (hawkeye) {
0549     case 0xb852:
0550         switch (rev) {
0551         case 0:
0552             omap_revision = OMAP4430_REV_ES1_0;
0553             break;
0554         case 1:
0555         default:
0556             omap_revision = OMAP4430_REV_ES2_0;
0557         }
0558         break;
0559     case 0xb95c:
0560         switch (rev) {
0561         case 3:
0562             omap_revision = OMAP4430_REV_ES2_1;
0563             break;
0564         case 4:
0565             omap_revision = OMAP4430_REV_ES2_2;
0566             break;
0567         case 6:
0568         default:
0569             omap_revision = OMAP4430_REV_ES2_3;
0570         }
0571         break;
0572     case 0xb94e:
0573         switch (rev) {
0574         case 0:
0575             omap_revision = OMAP4460_REV_ES1_0;
0576             break;
0577         case 2:
0578         default:
0579             omap_revision = OMAP4460_REV_ES1_1;
0580             break;
0581         }
0582         break;
0583     case 0xb975:
0584         switch (rev) {
0585         case 0:
0586         default:
0587             omap_revision = OMAP4470_REV_ES1_0;
0588             break;
0589         }
0590         break;
0591     default:
0592         /* Unknown default to latest silicon rev as default */
0593         omap_revision = OMAP4430_REV_ES2_3;
0594     }
0595 
0596     sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
0597     sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
0598                         (omap_rev() >> 8) & 0xf);
0599     pr_info("%s %s\n", soc_name, soc_rev);
0600 }
0601 
0602 void __init omap5xxx_check_revision(void)
0603 {
0604     u32 idcode;
0605     u16 hawkeye;
0606     u8 rev;
0607 
0608     idcode = read_tap_reg(OMAP_TAP_IDCODE);
0609     hawkeye = (idcode >> 12) & 0xffff;
0610     rev = (idcode >> 28) & 0xff;
0611     switch (hawkeye) {
0612     case 0xb942:
0613         switch (rev) {
0614         case 0:
0615             /* No support for ES1.0 Test chip */
0616             BUG();
0617         case 1:
0618         default:
0619             omap_revision = OMAP5430_REV_ES2_0;
0620         }
0621         break;
0622 
0623     case 0xb998:
0624         switch (rev) {
0625         case 0:
0626             /* No support for ES1.0 Test chip */
0627             BUG();
0628         case 1:
0629         default:
0630             omap_revision = OMAP5432_REV_ES2_0;
0631         }
0632         break;
0633 
0634     default:
0635         /* Unknown default to latest silicon rev as default*/
0636         omap_revision = OMAP5430_REV_ES2_0;
0637     }
0638 
0639     sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
0640     sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
0641 
0642     pr_info("%s %s\n", soc_name, soc_rev);
0643 }
0644 
0645 void __init dra7xxx_check_revision(void)
0646 {
0647     u32 idcode;
0648     u16 hawkeye;
0649     u8 rev, package;
0650     struct omap_die_id odi;
0651 
0652     omap_get_die_id(&odi);
0653     package = (odi.id_2 >> 16) & 0x3;
0654     idcode = read_tap_reg(OMAP_TAP_IDCODE);
0655     hawkeye = (idcode >> 12) & 0xffff;
0656     rev = (idcode >> 28) & 0xff;
0657     switch (hawkeye) {
0658     case 0xbb50:
0659         switch (rev) {
0660         case 0:
0661         default:
0662             switch (package) {
0663             case 0x2:
0664                 omap_revision = DRA762_ABZ_REV_ES1_0;
0665                 break;
0666             case 0x3:
0667                 omap_revision = DRA762_ACD_REV_ES1_0;
0668                 break;
0669             default:
0670                 omap_revision = DRA762_REV_ES1_0;
0671                 break;
0672             }
0673             break;
0674         }
0675         break;
0676 
0677     case 0xb990:
0678         switch (rev) {
0679         case 0:
0680             omap_revision = DRA752_REV_ES1_0;
0681             break;
0682         case 1:
0683             omap_revision = DRA752_REV_ES1_1;
0684             break;
0685         case 2:
0686         default:
0687             omap_revision = DRA752_REV_ES2_0;
0688             break;
0689         }
0690         break;
0691 
0692     case 0xb9bc:
0693         switch (rev) {
0694         case 0:
0695             omap_revision = DRA722_REV_ES1_0;
0696             break;
0697         case 1:
0698             omap_revision = DRA722_REV_ES2_0;
0699             break;
0700         case 2:
0701         default:
0702             omap_revision = DRA722_REV_ES2_1;
0703             break;
0704         }
0705         break;
0706 
0707     default:
0708         /* Unknown default to latest silicon rev as default*/
0709         pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
0710             __func__, idcode, hawkeye, rev);
0711         omap_revision = DRA752_REV_ES2_0;
0712     }
0713 
0714     sprintf(soc_name, "DRA%03x", omap_rev() >> 16);
0715     sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
0716         (omap_rev() >> 8) & 0xf);
0717 
0718     pr_info("%s %s\n", soc_name, soc_rev);
0719 }
0720 
0721 /*
0722  * Set up things for map_io and processor detection later on. Gets called
0723  * pretty much first thing from board init. For multi-omap, this gets
0724  * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
0725  * detect the exact revision later on in omap2_detect_revision() once map_io
0726  * is done.
0727  */
0728 void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
0729 {
0730     omap_revision = class;
0731     tap_base = tap;
0732 
0733     /* XXX What is this intended to do? */
0734     if (soc_is_omap34xx())
0735         tap_prod_id = 0x0210;
0736     else
0737         tap_prod_id = 0x0208;
0738 }
0739 
0740 #ifdef CONFIG_SOC_BUS
0741 
0742 static const char * const omap_types[] = {
0743     [OMAP2_DEVICE_TYPE_TEST]    = "TST",
0744     [OMAP2_DEVICE_TYPE_EMU]     = "EMU",
0745     [OMAP2_DEVICE_TYPE_SEC]     = "HS",
0746     [OMAP2_DEVICE_TYPE_GP]      = "GP",
0747     [OMAP2_DEVICE_TYPE_BAD]     = "BAD",
0748 };
0749 
0750 static const char * __init omap_get_family(void)
0751 {
0752     if (soc_is_omap24xx())
0753         return kasprintf(GFP_KERNEL, "OMAP2");
0754     else if (soc_is_omap34xx())
0755         return kasprintf(GFP_KERNEL, "OMAP3");
0756     else if (soc_is_omap44xx())
0757         return kasprintf(GFP_KERNEL, "OMAP4");
0758     else if (soc_is_omap54xx())
0759         return kasprintf(GFP_KERNEL, "OMAP5");
0760     else if (soc_is_am33xx() || soc_is_am335x())
0761         return kasprintf(GFP_KERNEL, "AM33xx");
0762     else if (soc_is_am43xx())
0763         return kasprintf(GFP_KERNEL, "AM43xx");
0764     else if (soc_is_dra7xx())
0765         return kasprintf(GFP_KERNEL, "DRA7");
0766     else
0767         return kasprintf(GFP_KERNEL, "Unknown");
0768 }
0769 
0770 static ssize_t
0771 type_show(struct device *dev, struct device_attribute *attr, char *buf)
0772 {
0773     return sprintf(buf, "%s\n", omap_types[omap_type()]);
0774 }
0775 
0776 static DEVICE_ATTR_RO(type);
0777 
0778 static struct attribute *omap_soc_attrs[] = {
0779     &dev_attr_type.attr,
0780     NULL
0781 };
0782 
0783 ATTRIBUTE_GROUPS(omap_soc);
0784 
0785 void __init omap_soc_device_init(void)
0786 {
0787     struct soc_device *soc_dev;
0788     struct soc_device_attribute *soc_dev_attr;
0789 
0790     soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
0791     if (!soc_dev_attr)
0792         return;
0793 
0794     soc_dev_attr->machine  = soc_name;
0795     soc_dev_attr->family   = omap_get_family();
0796     soc_dev_attr->revision = soc_rev;
0797     soc_dev_attr->custom_attr_group = omap_soc_groups[0];
0798 
0799     soc_dev = soc_device_register(soc_dev_attr);
0800     if (IS_ERR(soc_dev)) {
0801         kfree(soc_dev_attr);
0802         return;
0803     }
0804 }
0805 #endif /* CONFIG_SOC_BUS */
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