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0001 /*
0002  * arch/arm/mach-omap2/control.h
0003  *
0004  * OMAP2/3/4 System Control Module definitions
0005  *
0006  * Copyright (C) 2007-2010 Texas Instruments, Inc.
0007  * Copyright (C) 2007-2008, 2010 Nokia Corporation
0008  *
0009  * Written by Paul Walmsley
0010  *
0011  * This program is free software; you can redistribute it and/or modify
0012  * it under the terms of the GNU General Public License as published by
0013  * the Free Software Foundation.
0014  */
0015 
0016 #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
0017 #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
0018 
0019 #include "am33xx.h"
0020 
0021 #ifndef __ASSEMBLY__
0022 #define OMAP242X_CTRL_REGADDR(reg)                  \
0023         OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
0024 #define OMAP243X_CTRL_REGADDR(reg)                  \
0025         OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
0026 #define OMAP343X_CTRL_REGADDR(reg)                  \
0027         OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
0028 #define AM33XX_CTRL_REGADDR(reg)                    \
0029         AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
0030 #else
0031 #define OMAP242X_CTRL_REGADDR(reg)                  \
0032         OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
0033 #define OMAP243X_CTRL_REGADDR(reg)                  \
0034         OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
0035 #define OMAP343X_CTRL_REGADDR(reg)                  \
0036         OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
0037 #define AM33XX_CTRL_REGADDR(reg)                    \
0038         AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
0039 #endif /* __ASSEMBLY__ */
0040 
0041 /*
0042  * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
0043  * OMAP24XX and OMAP34XX.
0044  */
0045 
0046 /* Control submodule offsets */
0047 
0048 #define OMAP2_CONTROL_INTERFACE     0x000
0049 #define OMAP2_CONTROL_PADCONFS      0x030
0050 #define OMAP2_CONTROL_GENERAL       0x270
0051 #define OMAP343X_CONTROL_MEM_WKUP   0x600
0052 #define OMAP343X_CONTROL_PADCONFS_WKUP  0xa00
0053 #define OMAP343X_CONTROL_GENERAL_WKUP   0xa60
0054 
0055 /* TI81XX spefic control submodules */
0056 #define TI81XX_CONTROL_DEVBOOT      0x040
0057 #define TI81XX_CONTROL_DEVCONF      0x600
0058 
0059 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
0060 
0061 #define OMAP2_CONTROL_SYSCONFIG     (OMAP2_CONTROL_INTERFACE + 0x10)
0062 
0063 /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
0064 #define OMAP2_CONTROL_DEVCONF0      (OMAP2_CONTROL_GENERAL + 0x0004)
0065 #define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
0066 #define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
0067 #define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
0068 #define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
0069 #define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
0070 #define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
0071 #define OMAP2_CONTROL_SEC_CTRL      (OMAP2_CONTROL_GENERAL + 0x0040)
0072 #define OMAP2_CONTROL_RPUB_KEY_H_0  (OMAP2_CONTROL_GENERAL + 0x0090)
0073 #define OMAP2_CONTROL_RPUB_KEY_H_1  (OMAP2_CONTROL_GENERAL + 0x0094)
0074 #define OMAP2_CONTROL_RPUB_KEY_H_2  (OMAP2_CONTROL_GENERAL + 0x0098)
0075 #define OMAP2_CONTROL_RPUB_KEY_H_3  (OMAP2_CONTROL_GENERAL + 0x009c)
0076 
0077 /* 242x-only CONTROL_GENERAL register offsets */
0078 #define OMAP242X_CONTROL_DEVCONF    OMAP2_CONTROL_DEVCONF0 /* match TRM */
0079 #define OMAP242X_CONTROL_OCM_RAM_PERM   (OMAP2_CONTROL_GENERAL + 0x0068)
0080 
0081 /* 243x-only CONTROL_GENERAL register offsets */
0082 /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
0083 #define OMAP243X_CONTROL_DEVCONF1   (OMAP2_CONTROL_GENERAL + 0x0078)
0084 #define OMAP243X_CONTROL_CSIRXFE    (OMAP2_CONTROL_GENERAL + 0x007c)
0085 #define OMAP243X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
0086 #define OMAP243X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
0087 #define OMAP243X_CONTROL_IVA2_GEMCFG    (OMAP2_CONTROL_GENERAL + 0x0198)
0088 #define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
0089 
0090 /* 24xx-only CONTROL_GENERAL register offsets */
0091 #define OMAP24XX_CONTROL_DEBOBS     (OMAP2_CONTROL_GENERAL + 0x0000)
0092 #define OMAP24XX_CONTROL_EMU_SUPPORT    (OMAP2_CONTROL_GENERAL + 0x0008)
0093 #define OMAP24XX_CONTROL_SEC_TEST   (OMAP2_CONTROL_GENERAL + 0x0044)
0094 #define OMAP24XX_CONTROL_PSA_CTRL   (OMAP2_CONTROL_GENERAL + 0x0048)
0095 #define OMAP24XX_CONTROL_PSA_CMD    (OMAP2_CONTROL_GENERAL + 0x004c)
0096 #define OMAP24XX_CONTROL_PSA_VALUE  (OMAP2_CONTROL_GENERAL + 0x0050)
0097 #define OMAP24XX_CONTROL_SEC_EMU    (OMAP2_CONTROL_GENERAL + 0x0060)
0098 #define OMAP24XX_CONTROL_SEC_TAP    (OMAP2_CONTROL_GENERAL + 0x0064)
0099 #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD    (OMAP2_CONTROL_GENERAL + 0x006c)
0100 #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD  (OMAP2_CONTROL_GENERAL + 0x0070)
0101 #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD   (OMAP2_CONTROL_GENERAL + 0x0074)
0102 #define OMAP24XX_CONTROL_SEC_STATUS     (OMAP2_CONTROL_GENERAL + 0x0080)
0103 #define OMAP24XX_CONTROL_SEC_ERR_STATUS     (OMAP2_CONTROL_GENERAL + 0x0084)
0104 #define OMAP24XX_CONTROL_STATUS         (OMAP2_CONTROL_GENERAL + 0x0088)
0105 #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
0106 #define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
0107 #define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
0108 #define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
0109 #define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
0110 #define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
0111 #define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
0112 #define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
0113 #define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
0114 #define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
0115 #define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
0116 #define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
0117 #define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
0118 #define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
0119 #define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
0120 #define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
0121 #define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
0122 
0123 #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
0124 
0125 /* 34xx-only CONTROL_GENERAL register offsets */
0126 #define OMAP343X_CONTROL_PADCONF_OFF    (OMAP2_CONTROL_GENERAL + 0x0000)
0127 #define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
0128 #define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
0129 #define OMAP343X_CONTROL_DEVCONF1   (OMAP2_CONTROL_GENERAL + 0x0068)
0130 #define OMAP343X_CONTROL_CSIRXFE        (OMAP2_CONTROL_GENERAL + 0x006c)
0131 #define OMAP343X_CONTROL_SEC_STATUS     (OMAP2_CONTROL_GENERAL + 0x0070)
0132 #define OMAP343X_CONTROL_SEC_ERR_STATUS     (OMAP2_CONTROL_GENERAL + 0x0074)
0133 #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG   (OMAP2_CONTROL_GENERAL + 0x0078)
0134 #define OMAP343X_CONTROL_STATUS         (OMAP2_CONTROL_GENERAL + 0x0080)
0135 #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
0136 #define OMAP343X_CONTROL_RPUB_KEY_H_4   (OMAP2_CONTROL_GENERAL + 0x00a0)
0137 #define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
0138 #define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
0139 #define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
0140 #define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
0141 #define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
0142 #define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
0143 #define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
0144 #define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
0145 #define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
0146 #define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
0147 #define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
0148 #define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
0149 #define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
0150 #define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
0151 #define OMAP343X_CONTROL_TEST_KEY_10    (OMAP2_CONTROL_GENERAL + 0x00f0)
0152 #define OMAP343X_CONTROL_TEST_KEY_11    (OMAP2_CONTROL_GENERAL + 0x00f4)
0153 #define OMAP343X_CONTROL_TEST_KEY_12    (OMAP2_CONTROL_GENERAL + 0x00f8)
0154 #define OMAP343X_CONTROL_TEST_KEY_13    (OMAP2_CONTROL_GENERAL + 0x00fc)
0155 #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
0156 #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
0157 #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
0158 #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)
0159 #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
0160 #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)
0161 #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
0162 #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
0163 #define OMAP343X_CONTROL_FUSE_SR        (OMAP2_CONTROL_GENERAL + 0x0130)
0164 #define OMAP343X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
0165 #define OMAP343X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
0166 #define OMAP343X_CONTROL_DEBOBS(i)  (OMAP2_CONTROL_GENERAL + 0x01B0 \
0167                     + ((i) >> 1) * 4 + (!((i) & 1)) * 2)
0168 #define OMAP343X_CONTROL_PROG_IO0   (OMAP2_CONTROL_GENERAL + 0x01D4)
0169 #define OMAP343X_CONTROL_PROG_IO1   (OMAP2_CONTROL_GENERAL + 0x01D8)
0170 #define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
0171 #define OMAP343X_CONTROL_CORE_DPLL_SPREADING    (OMAP2_CONTROL_GENERAL + 0x01E4)
0172 #define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
0173 #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
0174 #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
0175 #define OMAP343X_CONTROL_TEMP_SENSOR    (OMAP2_CONTROL_GENERAL + 0x02B4)
0176 #define OMAP343X_CONTROL_SRAMLDO4   (OMAP2_CONTROL_GENERAL + 0x02B8)
0177 #define OMAP343X_CONTROL_SRAMLDO5   (OMAP2_CONTROL_GENERAL + 0x02C0)
0178 #define OMAP343X_CONTROL_CSI        (OMAP2_CONTROL_GENERAL + 0x02C4)
0179 
0180 /* OMAP3630 only CONTROL_GENERAL register offsets */
0181 #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1        (OMAP2_CONTROL_GENERAL + 0x0110)
0182 #define OMAP3630_CONTROL_FUSE_OPP50_VDD1        (OMAP2_CONTROL_GENERAL + 0x0114)
0183 #define OMAP3630_CONTROL_FUSE_OPP100_VDD1       (OMAP2_CONTROL_GENERAL + 0x0118)
0184 #define OMAP3630_CONTROL_FUSE_OPP120_VDD1       (OMAP2_CONTROL_GENERAL + 0x0120)
0185 #define OMAP3630_CONTROL_FUSE_OPP50_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)
0186 #define OMAP3630_CONTROL_FUSE_OPP100_VDD2       (OMAP2_CONTROL_GENERAL + 0x012C)
0187 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL    (OMAP2_CONTROL_GENERAL + 0x02f0)
0188 
0189 /* OMAP44xx control efuse offsets */
0190 #define OMAP44XX_CONTROL_FUSE_IVA_OPP50     0x22C
0191 #define OMAP44XX_CONTROL_FUSE_IVA_OPP100    0x22F
0192 #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO  0x232
0193 #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO  0x235
0194 #define OMAP44XX_CONTROL_FUSE_MPU_OPP50     0x240
0195 #define OMAP44XX_CONTROL_FUSE_MPU_OPP100    0x243
0196 #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO  0x246
0197 #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO  0x249
0198 #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITROSB    0x24C
0199 #define OMAP44XX_CONTROL_FUSE_CORE_OPP50    0x254
0200 #define OMAP44XX_CONTROL_FUSE_CORE_OPP100   0x257
0201 #define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV 0x25A
0202 
0203 /* AM35XX only CONTROL_GENERAL register offsets */
0204 #define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
0205 #define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
0206 #define AM35XX_CONTROL_DEVCONF3         (OMAP2_CONTROL_GENERAL + 0x0314)
0207 #define AM35XX_CONTROL_CBA_PRIORITY     (OMAP2_CONTROL_GENERAL + 0x0320)
0208 #define AM35XX_CONTROL_LVL_INTR_CLEAR   (OMAP2_CONTROL_GENERAL + 0x0324)
0209 #define AM35XX_CONTROL_IP_SW_RESET      (OMAP2_CONTROL_GENERAL + 0x0328)
0210 #define AM35XX_CONTROL_IPSS_CLK_CTRL    (OMAP2_CONTROL_GENERAL + 0x032C)
0211 
0212 /* 34xx PADCONF register offsets */
0213 #define OMAP343X_PADCONF_ETK(i)     (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
0214                         (i)*2)
0215 #define OMAP343X_PADCONF_ETK_CLK    OMAP343X_PADCONF_ETK(0)
0216 #define OMAP343X_PADCONF_ETK_CTL    OMAP343X_PADCONF_ETK(1)
0217 #define OMAP343X_PADCONF_ETK_D0     OMAP343X_PADCONF_ETK(2)
0218 #define OMAP343X_PADCONF_ETK_D1     OMAP343X_PADCONF_ETK(3)
0219 #define OMAP343X_PADCONF_ETK_D2     OMAP343X_PADCONF_ETK(4)
0220 #define OMAP343X_PADCONF_ETK_D3     OMAP343X_PADCONF_ETK(5)
0221 #define OMAP343X_PADCONF_ETK_D4     OMAP343X_PADCONF_ETK(6)
0222 #define OMAP343X_PADCONF_ETK_D5     OMAP343X_PADCONF_ETK(7)
0223 #define OMAP343X_PADCONF_ETK_D6     OMAP343X_PADCONF_ETK(8)
0224 #define OMAP343X_PADCONF_ETK_D7     OMAP343X_PADCONF_ETK(9)
0225 #define OMAP343X_PADCONF_ETK_D8     OMAP343X_PADCONF_ETK(10)
0226 #define OMAP343X_PADCONF_ETK_D9     OMAP343X_PADCONF_ETK(11)
0227 #define OMAP343X_PADCONF_ETK_D10    OMAP343X_PADCONF_ETK(12)
0228 #define OMAP343X_PADCONF_ETK_D11    OMAP343X_PADCONF_ETK(13)
0229 #define OMAP343X_PADCONF_ETK_D12    OMAP343X_PADCONF_ETK(14)
0230 #define OMAP343X_PADCONF_ETK_D13    OMAP343X_PADCONF_ETK(15)
0231 #define OMAP343X_PADCONF_ETK_D14    OMAP343X_PADCONF_ETK(16)
0232 #define OMAP343X_PADCONF_ETK_D15    OMAP343X_PADCONF_ETK(17)
0233 
0234 /* 34xx GENERAL_WKUP register offsets */
0235 #define OMAP34XX_CONTROL_WKUP_CTRL  (OMAP343X_CONTROL_GENERAL_WKUP - 0x4)
0236 #define OMAP36XX_GPIO_IO_PWRDNZ     BIT(6)
0237 
0238 #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
0239                         0x008 + (i))
0240 #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
0241 #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
0242 #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
0243 #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
0244 #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
0245 
0246 /* 36xx-only RTA - Retention till Access control registers and bits */
0247 #define OMAP36XX_CONTROL_MEM_RTA_CTRL   0x40C
0248 #define OMAP36XX_RTA_DISABLE        0x0
0249 
0250 /* 34xx D2D idle-related pins, handled by PM core */
0251 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
0252 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
0253 
0254 /* TI81XX CONTROL_DEVBOOT register offsets */
0255 #define TI81XX_CONTROL_STATUS       (TI81XX_CONTROL_DEVBOOT + 0x000)
0256 
0257 /* TI81XX CONTROL_DEVCONF register offsets */
0258 #define TI81XX_CONTROL_DEVICE_ID    (TI81XX_CONTROL_DEVCONF + 0x000)
0259 
0260 /* OMAP4 CONTROL MODULE */
0261 #define OMAP4_CTRL_MODULE_PAD_WKUP          0x4a31e000
0262 #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2    0x0604
0263 #define OMAP4_CTRL_MODULE_CORE_STATUS           0x02c4
0264 #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1   0x0218
0265 #define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR     0x0304
0266 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY   0x0618
0267 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX    0x0608
0268 
0269 /* OMAP4 CONTROL_DSIPHY */
0270 #define OMAP4_DSI2_LANEENABLE_SHIFT         29
0271 #define OMAP4_DSI2_LANEENABLE_MASK          (0x7 << 29)
0272 #define OMAP4_DSI1_LANEENABLE_SHIFT         24
0273 #define OMAP4_DSI1_LANEENABLE_MASK          (0x1f << 24)
0274 #define OMAP4_DSI1_PIPD_SHIFT               19
0275 #define OMAP4_DSI1_PIPD_MASK                (0x1f << 19)
0276 #define OMAP4_DSI2_PIPD_SHIFT               14
0277 #define OMAP4_DSI2_PIPD_MASK                (0x1f << 14)
0278 
0279 /* OMAP4 CONTROL_CAMERA_RX */
0280 #define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT       24
0281 #define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK        (0x1f << 24)
0282 #define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT       29
0283 #define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK        (0x3 << 29)
0284 #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT        21
0285 #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK     (1 << 21)
0286 #define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT      19
0287 #define OMAP4_CAMERARX_CSI22_CAMMODE_MASK       (0x3 << 19)
0288 #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT        18
0289 #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK     (1 << 18)
0290 #define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT      16
0291 #define OMAP4_CAMERARX_CSI21_CAMMODE_MASK       (0x3 << 16)
0292 
0293 /* OMAP54XX CONTROL STATUS register */
0294 #define OMAP5XXX_CONTROL_STATUS                0x134
0295 #define OMAP5_DEVICETYPE_MASK          (0x7 << 6)
0296 
0297 /* DRA7XX CONTROL CORE BOOTSTRAP */
0298 #define DRA7_CTRL_CORE_BOOTSTRAP    0x6c4
0299 #define DRA7_SPEEDSELECT_MASK       (0x3 << 8)
0300 
0301 /*
0302  * REVISIT: This list of registers is not comprehensive - there are more
0303  * that should be added.
0304  */
0305 
0306 /*
0307  * Control module register bit defines - these should eventually go into
0308  * their own regbits file.  Some of these will be complicated, depending
0309  * on the device type (general-purpose, emulator, test, secure, bad, other)
0310  * and the security mode (secure, non-secure, don't care)
0311  */
0312 /* CONTROL_DEVCONF0 bits */
0313 #define OMAP2_MMCSDIO1ADPCLKISEL    (1 << 24) /* MMC1 loop back clock */
0314 #define OMAP24XX_USBSTANDBYCTRL     (1 << 15)
0315 #define OMAP2_MCBSP2_CLKS_MASK      (1 << 6)
0316 #define OMAP2_MCBSP1_FSR_MASK       (1 << 4)
0317 #define OMAP2_MCBSP1_CLKR_MASK      (1 << 3)
0318 #define OMAP2_MCBSP1_CLKS_MASK      (1 << 2)
0319 
0320 /* CONTROL_DEVCONF1 bits */
0321 #define OMAP243X_MMC1_ACTIVE_OVERWRITE  (1 << 31)
0322 #define OMAP2_MMCSDIO2ADPCLKISEL    (1 << 6) /* MMC2 loop back clock */
0323 #define OMAP2_MCBSP5_CLKS_MASK      (1 << 4) /* > 242x */
0324 #define OMAP2_MCBSP4_CLKS_MASK      (1 << 2) /* > 242x */
0325 #define OMAP2_MCBSP3_CLKS_MASK      (1 << 0) /* > 242x */
0326 
0327 /* CONTROL_STATUS bits */
0328 #define OMAP2_DEVICETYPE_MASK       (0x7 << 8)
0329 #define OMAP2_SYSBOOT_5_MASK        (1 << 5)
0330 #define OMAP2_SYSBOOT_4_MASK        (1 << 4)
0331 #define OMAP2_SYSBOOT_3_MASK        (1 << 3)
0332 #define OMAP2_SYSBOOT_2_MASK        (1 << 2)
0333 #define OMAP2_SYSBOOT_1_MASK        (1 << 1)
0334 #define OMAP2_SYSBOOT_0_MASK        (1 << 0)
0335 
0336 /* CONTROL_PBIAS_LITE bits */
0337 #define OMAP343X_PBIASLITESUPPLY_HIGH1  (1 << 15)
0338 #define OMAP343X_PBIASLITEVMODEERROR1   (1 << 11)
0339 #define OMAP343X_PBIASSPEEDCTRL1    (1 << 10)
0340 #define OMAP343X_PBIASLITEPWRDNZ1   (1 << 9)
0341 #define OMAP343X_PBIASLITEVMODE1    (1 << 8)
0342 #define OMAP343X_PBIASLITESUPPLY_HIGH0  (1 << 7)
0343 #define OMAP343X_PBIASLITEVMODEERROR0   (1 << 3)
0344 #define OMAP2_PBIASSPEEDCTRL0       (1 << 2)
0345 #define OMAP2_PBIASLITEPWRDNZ0      (1 << 1)
0346 #define OMAP2_PBIASLITEVMODE0       (1 << 0)
0347 
0348 /* CONTROL_PROG_IO1 bits */
0349 #define OMAP3630_PRG_SDMMC1_SPEEDCTRL   (1 << 20)
0350 
0351 /* CONTROL_IVA2_BOOTMOD bits */
0352 #define OMAP3_IVA2_BOOTMOD_SHIFT    0
0353 #define OMAP3_IVA2_BOOTMOD_MASK     (0xf << 0)
0354 #define OMAP3_IVA2_BOOTMOD_IDLE     (0x1 << 0)
0355 
0356 /* CONTROL_PADCONF_X bits */
0357 #define OMAP3_PADCONF_WAKEUPEVENT0  (1 << 15)
0358 #define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
0359 
0360 #define OMAP343X_SCRATCHPAD_ROM     (OMAP343X_CTRL_BASE + 0x860)
0361 #define OMAP343X_SCRATCHPAD     (OMAP343X_CTRL_BASE + 0x910)
0362 #define OMAP343X_SCRATCHPAD_ROM_OFFSET  0x19C
0363 #define OMAP343X_SCRATCHPAD_REGADDR(reg)    OMAP2_L4_IO_ADDRESS(\
0364                         OMAP343X_SCRATCHPAD + reg)
0365 
0366 /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
0367 #define AM35XX_USBOTG_VBUSP_CLK_SHIFT   0
0368 #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT   1
0369 #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
0370 #define AM35XX_HECC_VBUSP_CLK_SHIFT 3
0371 #define AM35XX_USBOTG_FCLK_SHIFT    8
0372 #define AM35XX_CPGMAC_FCLK_SHIFT    9
0373 #define AM35XX_VPFE_FCLK_SHIFT      10
0374 
0375 /* AM35XX CONTROL_LVL_INTR_CLEAR bits */
0376 #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
0377 #define AM35XX_CPGMAC_C0_RX_PULSE_CLR   BIT(1)
0378 #define AM35XX_CPGMAC_C0_RX_THRESH_CLR  BIT(2)
0379 #define AM35XX_CPGMAC_C0_TX_PULSE_CLR   BIT(3)
0380 #define AM35XX_USBOTGSS_INT_CLR     BIT(4)
0381 #define AM35XX_VPFE_CCDC_VD0_INT_CLR    BIT(5)
0382 #define AM35XX_VPFE_CCDC_VD1_INT_CLR    BIT(6)
0383 #define AM35XX_VPFE_CCDC_VD2_INT_CLR    BIT(7)
0384 
0385 /* AM35XX CONTROL_IP_SW_RESET bits */
0386 #define AM35XX_USBOTGSS_SW_RST      BIT(0)
0387 #define AM35XX_CPGMACSS_SW_RST      BIT(1)
0388 #define AM35XX_VPFE_VBUSP_SW_RST    BIT(2)
0389 #define AM35XX_HECC_SW_RST      BIT(3)
0390 #define AM35XX_VPFE_PCLK_SW_RST     BIT(4)
0391 
0392 /* AM33XX CONTROL_STATUS register */
0393 #define AM33XX_CONTROL_STATUS       0x040
0394 #define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc
0395 
0396 /* AM33XX CONTROL_STATUS bitfields (partial) */
0397 #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT        22
0398 #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH        0x2
0399 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK     (0x3 << 22)
0400 
0401 /* AM33XX PWMSS Control register */
0402 #define AM33XX_PWMSS_TBCLK_CLKCTRL          0x664
0403 
0404 /* AM33XX  PWMSS Control bitfields */
0405 #define AM33XX_PWMSS0_TBCLKEN_SHIFT         0
0406 #define AM33XX_PWMSS1_TBCLKEN_SHIFT         1
0407 #define AM33XX_PWMSS2_TBCLKEN_SHIFT         2
0408 
0409 /* DEV Feature register to identify AM33XX features */
0410 #define AM33XX_DEV_FEATURE      0x604
0411 #define AM33XX_SGX_MASK         BIT(29)
0412 
0413 /* Additional AM33XX/AM43XX CONTROL registers */
0414 #define AM33XX_CONTROL_SYSCONFIG_OFFSET         0x0010
0415 #define AM33XX_CONTROL_STATUS_OFFSET            0x0040
0416 #define AM43XX_CONTROL_MPU_L2_CTRL_OFFSET       0x01e0
0417 #define AM33XX_CONTROL_CORTEX_VBBLDO_CTRL_OFFSET    0x041c
0418 #define AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET        0x0428
0419 #define AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET     0x042c
0420 #define AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET   0x0444
0421 #define AM33XX_CONTROL_BANDGAP_CTRL_OFFSET      0x0448
0422 #define AM33XX_CONTROL_BANDGAP_TRIM_OFFSET      0x044c
0423 #define AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET   0x0458
0424 #define AM33XX_CONTROL_MOSC_CTRL_OFFSET         0x0468
0425 #define AM33XX_CONTROL_RCOSC_CTRL_OFFSET        0x046c
0426 #define AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET        0x0470
0427 #define AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET       0x0534
0428 #define AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET       0x0608
0429 #define AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET       0x060c
0430 #define AM33XX_CONTROL_MMU_CFG_OFFSET           0x0610
0431 #define AM33XX_CONTROL_TPTC_CFG_OFFSET          0x0614
0432 #define AM33XX_CONTROL_USB_CTRL0_OFFSET         0x0620
0433 #define AM33XX_CONTROL_USB_CTRL1_OFFSET         0x0628
0434 #define AM33XX_CONTROL_USB_WKUP_CTRL_OFFSET     0x0648
0435 #define AM43XX_CONTROL_USB_CTRL2_OFFSET         0x064c
0436 #define AM43XX_CONTROL_GMII_SEL_OFFSET          0x0650
0437 #define AM43XX_CONTROL_MPUSS_CTRL_OFFSET        0x0654
0438 #define AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET    0x0658
0439 #define AM43XX_CONTROL_PWMSS_CTRL_OFFSET        0x0664
0440 #define AM33XX_CONTROL_MREQPRIO_0_OFFSET        0x0670
0441 #define AM33XX_CONTROL_MREQPRIO_1_OFFSET        0x0674
0442 #define AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET     0x0690
0443 #define AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET     0x0694
0444 #define AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET     0x0698
0445 #define AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET     0x069c
0446 #define AM33XX_CONTROL_SMRT_CTRL_OFFSET         0x06a0
0447 #define AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET    0x06a4
0448 #define AM43XX_CONTROL_CQDETECT_STS_OFFSET      0x0e00
0449 #define AM43XX_CONTROL_CQDETECT_STS2_OFFSET     0x0e08
0450 #define AM43XX_CONTROL_VTP_CTRL_OFFSET          0x0e0c
0451 #define AM33XX_CONTROL_VREF_CTRL_OFFSET         0x0e14
0452 #define AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET      0x0f90
0453 #define AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET      0x0f94
0454 #define AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET     0x0f98
0455 #define AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET    0x0f9c
0456 #define AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET    0x0fa0
0457 #define AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET    0x0fa4
0458 #define AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET    0x0fa8
0459 #define AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET    0x0fac
0460 #define AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET    0x0fb0
0461 #define AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET    0x0fb4
0462 #define AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET    0x0fb8
0463 #define AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET    0x0fbc
0464 #define AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET    0x0fc0
0465 #define AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET    0x0fc4
0466 #define AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET    0x0fc8
0467 #define AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET    0x0fcc
0468 #define AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET        0x0fd0
0469 #define AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET     0x0fd4
0470 #define AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET      0x0fd8
0471 #define AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET     0x0fdc
0472 #define AM33XX_CONTROL_RESET_ISO_OFFSET         0x1000
0473 
0474 /* CONTROL OMAP STATUS register to identify OMAP3 features */
0475 #define OMAP3_CONTROL_OMAP_STATUS   0x044c
0476 
0477 #define OMAP3_SGX_SHIFT         13
0478 #define OMAP3_SGX_MASK          (3 << OMAP3_SGX_SHIFT)
0479 #define     FEAT_SGX_FULL       0
0480 #define     FEAT_SGX_HALF       1
0481 #define     FEAT_SGX_NONE       2
0482 
0483 #define OMAP3_IVA_SHIFT         12
0484 #define OMAP3_IVA_MASK          (1 << OMAP3_IVA_SHIFT)
0485 #define     FEAT_IVA        0
0486 #define     FEAT_IVA_NONE       1
0487 
0488 #define OMAP3_L2CACHE_SHIFT     10
0489 #define OMAP3_L2CACHE_MASK      (3 << OMAP3_L2CACHE_SHIFT)
0490 #define     FEAT_L2CACHE_NONE   0
0491 #define     FEAT_L2CACHE_64KB   1
0492 #define     FEAT_L2CACHE_128KB  2
0493 #define     FEAT_L2CACHE_256KB  3
0494 
0495 #define OMAP3_ISP_SHIFT         5
0496 #define OMAP3_ISP_MASK          (1 << OMAP3_ISP_SHIFT)
0497 #define     FEAT_ISP        0
0498 #define     FEAT_ISP_NONE       1
0499 
0500 #define OMAP3_NEON_SHIFT        4
0501 #define OMAP3_NEON_MASK         (1 << OMAP3_NEON_SHIFT)
0502 #define     FEAT_NEON       0
0503 #define     FEAT_NEON_NONE      1
0504 
0505 
0506 #ifndef __ASSEMBLY__
0507 #ifdef CONFIG_ARCH_OMAP2PLUS
0508 extern u8 omap_ctrl_readb(u16 offset);
0509 extern u16 omap_ctrl_readw(u16 offset);
0510 extern u32 omap_ctrl_readl(u16 offset);
0511 extern void omap_ctrl_writeb(u8 val, u16 offset);
0512 extern void omap_ctrl_writew(u16 val, u16 offset);
0513 extern void omap_ctrl_writel(u32 val, u16 offset);
0514 
0515 extern void omap3_save_scratchpad_contents(void);
0516 extern void omap3_clear_scratchpad_contents(void);
0517 extern void omap3_restore(void);
0518 extern void omap3_restore_es3(void);
0519 extern void omap3_restore_3630(void);
0520 extern u32 omap3_arm_context[128];
0521 extern void omap3_control_save_context(void);
0522 extern void omap3_control_restore_context(void);
0523 extern void omap3_ctrl_write_boot_mode(u8 bootmode);
0524 extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
0525 extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
0526 extern void omap3630_ctrl_disable_rta(void);
0527 extern int omap3_ctrl_save_padconf(void);
0528 void omap3_ctrl_init(void);
0529 int omap2_control_base_init(void);
0530 int omap_control_init(void);
0531 void __init omap3_control_legacy_iomap_init(void);
0532 #else
0533 #define omap_ctrl_readb(x)      0
0534 #define omap_ctrl_readw(x)      0
0535 #define omap_ctrl_readl(x)      0
0536 #define omap4_ctrl_pad_readl(x)     0
0537 #define omap_ctrl_writeb(x, y)      WARN_ON(1)
0538 #define omap_ctrl_writew(x, y)      WARN_ON(1)
0539 #define omap_ctrl_writel(x, y)      WARN_ON(1)
0540 #define omap4_ctrl_pad_writel(x, y) WARN_ON(1)
0541 #endif
0542 #endif  /* __ASSEMBLY__ */
0543 
0544 #endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */
0545
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