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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * OMAP2/3 System Control Module register access
0004  *
0005  * Copyright (C) 2007, 2012 Texas Instruments, Inc.
0006  * Copyright (C) 2007 Nokia Corporation
0007  *
0008  * Written by Paul Walmsley
0009  */
0010 #undef DEBUG
0011 
0012 #include <linux/kernel.h>
0013 #include <linux/io.h>
0014 #include <linux/of_address.h>
0015 #include <linux/regmap.h>
0016 #include <linux/mfd/syscon.h>
0017 #include <linux/cpu_pm.h>
0018 
0019 #include "soc.h"
0020 #include "iomap.h"
0021 #include "common.h"
0022 #include "cm-regbits-34xx.h"
0023 #include "prm-regbits-34xx.h"
0024 #include "prm3xxx.h"
0025 #include "cm3xxx.h"
0026 #include "sdrc.h"
0027 #include "pm.h"
0028 #include "control.h"
0029 #include "clock.h"
0030 
0031 /* Used by omap3_ctrl_save_padconf() */
0032 #define START_PADCONF_SAVE      0x2
0033 #define PADCONF_SAVE_DONE       0x1
0034 
0035 static void __iomem *omap2_ctrl_base;
0036 static s16 omap2_ctrl_offset;
0037 
0038 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
0039 struct omap3_scratchpad {
0040     u32 boot_config_ptr;
0041     u32 public_restore_ptr;
0042     u32 secure_ram_restore_ptr;
0043     u32 sdrc_module_semaphore;
0044     u32 prcm_block_offset;
0045     u32 sdrc_block_offset;
0046 };
0047 
0048 struct omap3_scratchpad_prcm_block {
0049     u32 prm_contents[2];
0050     u32 cm_contents[11];
0051     u32 prcm_block_size;
0052 };
0053 
0054 struct omap3_scratchpad_sdrc_block {
0055     u16 sysconfig;
0056     u16 cs_cfg;
0057     u16 sharing;
0058     u16 err_type;
0059     u32 dll_a_ctrl;
0060     u32 dll_b_ctrl;
0061     u32 power;
0062     u32 cs_0;
0063     u32 mcfg_0;
0064     u16 mr_0;
0065     u16 emr_1_0;
0066     u16 emr_2_0;
0067     u16 emr_3_0;
0068     u32 actim_ctrla_0;
0069     u32 actim_ctrlb_0;
0070     u32 rfr_ctrl_0;
0071     u32 cs_1;
0072     u32 mcfg_1;
0073     u16 mr_1;
0074     u16 emr_1_1;
0075     u16 emr_2_1;
0076     u16 emr_3_1;
0077     u32 actim_ctrla_1;
0078     u32 actim_ctrlb_1;
0079     u32 rfr_ctrl_1;
0080     u16 dcdl_1_ctrl;
0081     u16 dcdl_2_ctrl;
0082     u32 flags;
0083     u32 block_size;
0084 };
0085 
0086 void *omap3_secure_ram_storage;
0087 
0088 /*
0089  * This is used to store ARM registers in SDRAM before attempting
0090  * an MPU OFF. The save and restore happens from the SRAM sleep code.
0091  * The address is stored in scratchpad, so that it can be used
0092  * during the restore path.
0093  */
0094 u32 omap3_arm_context[128];
0095 
0096 struct omap3_control_regs {
0097     u32 sysconfig;
0098     u32 devconf0;
0099     u32 mem_dftrw0;
0100     u32 mem_dftrw1;
0101     u32 msuspendmux_0;
0102     u32 msuspendmux_1;
0103     u32 msuspendmux_2;
0104     u32 msuspendmux_3;
0105     u32 msuspendmux_4;
0106     u32 msuspendmux_5;
0107     u32 sec_ctrl;
0108     u32 devconf1;
0109     u32 csirxfe;
0110     u32 iva2_bootaddr;
0111     u32 iva2_bootmod;
0112     u32 wkup_ctrl;
0113     u32 debobs_0;
0114     u32 debobs_1;
0115     u32 debobs_2;
0116     u32 debobs_3;
0117     u32 debobs_4;
0118     u32 debobs_5;
0119     u32 debobs_6;
0120     u32 debobs_7;
0121     u32 debobs_8;
0122     u32 prog_io0;
0123     u32 prog_io1;
0124     u32 dss_dpll_spreading;
0125     u32 core_dpll_spreading;
0126     u32 per_dpll_spreading;
0127     u32 usbhost_dpll_spreading;
0128     u32 pbias_lite;
0129     u32 temp_sensor;
0130     u32 sramldo4;
0131     u32 sramldo5;
0132     u32 csi;
0133     u32 padconf_sys_nirq;
0134 };
0135 
0136 static struct omap3_control_regs control_context;
0137 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
0138 
0139 u8 omap_ctrl_readb(u16 offset)
0140 {
0141     u32 val;
0142     u8 byte_offset = offset & 0x3;
0143 
0144     val = omap_ctrl_readl(offset);
0145 
0146     return (val >> (byte_offset * 8)) & 0xff;
0147 }
0148 
0149 u16 omap_ctrl_readw(u16 offset)
0150 {
0151     u32 val;
0152     u16 byte_offset = offset & 0x2;
0153 
0154     val = omap_ctrl_readl(offset);
0155 
0156     return (val >> (byte_offset * 8)) & 0xffff;
0157 }
0158 
0159 u32 omap_ctrl_readl(u16 offset)
0160 {
0161     offset &= 0xfffc;
0162 
0163     return readl_relaxed(omap2_ctrl_base + offset);
0164 }
0165 
0166 void omap_ctrl_writeb(u8 val, u16 offset)
0167 {
0168     u32 tmp;
0169     u8 byte_offset = offset & 0x3;
0170 
0171     tmp = omap_ctrl_readl(offset);
0172 
0173     tmp &= 0xffffffff ^ (0xff << (byte_offset * 8));
0174     tmp |= val << (byte_offset * 8);
0175 
0176     omap_ctrl_writel(tmp, offset);
0177 }
0178 
0179 void omap_ctrl_writew(u16 val, u16 offset)
0180 {
0181     u32 tmp;
0182     u8 byte_offset = offset & 0x2;
0183 
0184     tmp = omap_ctrl_readl(offset);
0185 
0186     tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8));
0187     tmp |= val << (byte_offset * 8);
0188 
0189     omap_ctrl_writel(tmp, offset);
0190 }
0191 
0192 void omap_ctrl_writel(u32 val, u16 offset)
0193 {
0194     offset &= 0xfffc;
0195     writel_relaxed(val, omap2_ctrl_base + offset);
0196 }
0197 
0198 #ifdef CONFIG_ARCH_OMAP3
0199 
0200 /**
0201  * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
0202  * @bootmode: 8-bit value to pass to some boot code
0203  *
0204  * Set the bootmode in the scratchpad RAM.  This is used after the
0205  * system restarts.  Not sure what actually uses this - it may be the
0206  * bootloader, rather than the boot ROM - contrary to the preserved
0207  * comment below.  No return value.
0208  */
0209 void omap3_ctrl_write_boot_mode(u8 bootmode)
0210 {
0211     u32 l;
0212 
0213     l = ('B' << 24) | ('M' << 16) | bootmode;
0214 
0215     /*
0216      * Reserve the first word in scratchpad for communicating
0217      * with the boot ROM. A pointer to a data structure
0218      * describing the boot process can be stored there,
0219      * cf. OMAP34xx TRM, Initialization / Software Booting
0220      * Configuration.
0221      *
0222      * XXX This should use some omap_ctrl_writel()-type function
0223      */
0224     writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
0225 }
0226 
0227 #endif
0228 
0229 /**
0230  * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
0231  * @bootaddr: physical address of the boot loader
0232  *
0233  * Set boot address for the boot loader of a supported processor
0234  * when a power ON sequence occurs.
0235  */
0236 void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
0237 {
0238     u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
0239              cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
0240              cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
0241              soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
0242              0;
0243 
0244     if (!offset) {
0245         pr_err("%s: unsupported omap type\n", __func__);
0246         return;
0247     }
0248 
0249     omap_ctrl_writel(bootaddr, offset);
0250 }
0251 
0252 /**
0253  * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
0254  * @bootmode: 8-bit value to pass to some boot code
0255  *
0256  * Sets boot mode for the boot loader of a supported processor
0257  * when a power ON sequence occurs.
0258  */
0259 void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
0260 {
0261     u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
0262              cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
0263              0;
0264 
0265     if (!offset) {
0266         pr_err("%s: unsupported omap type\n", __func__);
0267         return;
0268     }
0269 
0270     omap_ctrl_writel(bootmode, offset);
0271 }
0272 
0273 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
0274 /*
0275  * Clears the scratchpad contents in case of cold boot-
0276  * called during bootup
0277  */
0278 void omap3_clear_scratchpad_contents(void)
0279 {
0280     u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
0281     void __iomem *v_addr;
0282     u32 offset = 0;
0283 
0284     v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
0285     if (omap3xxx_prm_clear_global_cold_reset()) {
0286         for ( ; offset <= max_offset; offset += 0x4)
0287             writel_relaxed(0x0, (v_addr + offset));
0288     }
0289 }
0290 
0291 /* Populate the scratchpad structure with restore structure */
0292 void omap3_save_scratchpad_contents(void)
0293 {
0294     void  __iomem *scratchpad_address;
0295     u32 arm_context_addr;
0296     struct omap3_scratchpad scratchpad_contents;
0297     struct omap3_scratchpad_prcm_block prcm_block_contents;
0298     struct omap3_scratchpad_sdrc_block sdrc_block_contents;
0299 
0300     /*
0301      * Populate the Scratchpad contents
0302      *
0303      * The "get_*restore_pointer" functions are used to provide a
0304      * physical restore address where the ROM code jumps while waking
0305      * up from MPU OFF/OSWR state.
0306      * The restore pointer is stored into the scratchpad.
0307      */
0308     scratchpad_contents.boot_config_ptr = 0x0;
0309     if (cpu_is_omap3630())
0310         scratchpad_contents.public_restore_ptr =
0311             __pa_symbol(omap3_restore_3630);
0312     else if (omap_rev() != OMAP3430_REV_ES3_0 &&
0313                     omap_rev() != OMAP3430_REV_ES3_1 &&
0314                     omap_rev() != OMAP3430_REV_ES3_1_2)
0315         scratchpad_contents.public_restore_ptr =
0316             __pa_symbol(omap3_restore);
0317     else
0318         scratchpad_contents.public_restore_ptr =
0319             __pa_symbol(omap3_restore_es3);
0320 
0321     if (omap_type() == OMAP2_DEVICE_TYPE_GP)
0322         scratchpad_contents.secure_ram_restore_ptr = 0x0;
0323     else
0324         scratchpad_contents.secure_ram_restore_ptr =
0325             (u32) __pa(omap3_secure_ram_storage);
0326     scratchpad_contents.sdrc_module_semaphore = 0x0;
0327     scratchpad_contents.prcm_block_offset = 0x2C;
0328     scratchpad_contents.sdrc_block_offset = 0x64;
0329 
0330     /* Populate the PRCM block contents */
0331     omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents);
0332     omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
0333 
0334     prcm_block_contents.prcm_block_size = 0x0;
0335 
0336     /* Populate the SDRC block contents */
0337     sdrc_block_contents.sysconfig =
0338             (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
0339     sdrc_block_contents.cs_cfg =
0340             (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
0341     sdrc_block_contents.sharing =
0342             (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
0343     sdrc_block_contents.err_type =
0344             (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
0345     sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
0346     sdrc_block_contents.dll_b_ctrl = 0x0;
0347     /*
0348      * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
0349      * be programed to issue automatic self refresh on timeout
0350      * of AUTO_CNT = 1 prior to any transition to OFF mode.
0351      */
0352     if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
0353             && (omap_rev() >= OMAP3430_REV_ES3_0))
0354         sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
0355                 ~(SDRC_POWER_AUTOCOUNT_MASK|
0356                 SDRC_POWER_CLKCTRL_MASK)) |
0357                 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
0358                 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
0359     else
0360         sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
0361 
0362     sdrc_block_contents.cs_0 = 0x0;
0363     sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
0364     sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
0365     sdrc_block_contents.emr_1_0 = 0x0;
0366     sdrc_block_contents.emr_2_0 = 0x0;
0367     sdrc_block_contents.emr_3_0 = 0x0;
0368     sdrc_block_contents.actim_ctrla_0 =
0369             sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
0370     sdrc_block_contents.actim_ctrlb_0 =
0371             sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
0372     sdrc_block_contents.rfr_ctrl_0 =
0373             sdrc_read_reg(SDRC_RFR_CTRL_0);
0374     sdrc_block_contents.cs_1 = 0x0;
0375     sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
0376     sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
0377     sdrc_block_contents.emr_1_1 = 0x0;
0378     sdrc_block_contents.emr_2_1 = 0x0;
0379     sdrc_block_contents.emr_3_1 = 0x0;
0380     sdrc_block_contents.actim_ctrla_1 =
0381             sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
0382     sdrc_block_contents.actim_ctrlb_1 =
0383             sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
0384     sdrc_block_contents.rfr_ctrl_1 =
0385             sdrc_read_reg(SDRC_RFR_CTRL_1);
0386     sdrc_block_contents.dcdl_1_ctrl = 0x0;
0387     sdrc_block_contents.dcdl_2_ctrl = 0x0;
0388     sdrc_block_contents.flags = 0x0;
0389     sdrc_block_contents.block_size = 0x0;
0390 
0391     arm_context_addr = __pa_symbol(omap3_arm_context);
0392 
0393     /* Copy all the contents to the scratchpad location */
0394     scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
0395     memcpy_toio(scratchpad_address, &scratchpad_contents,
0396          sizeof(scratchpad_contents));
0397     /* Scratchpad contents being 32 bits, a divide by 4 done here */
0398     memcpy_toio(scratchpad_address +
0399         scratchpad_contents.prcm_block_offset,
0400         &prcm_block_contents, sizeof(prcm_block_contents));
0401     memcpy_toio(scratchpad_address +
0402         scratchpad_contents.sdrc_block_offset,
0403         &sdrc_block_contents, sizeof(sdrc_block_contents));
0404     /*
0405      * Copies the address of the location in SDRAM where ARM
0406      * registers get saved during a MPU OFF transition.
0407      */
0408     memcpy_toio(scratchpad_address +
0409         scratchpad_contents.sdrc_block_offset +
0410         sizeof(sdrc_block_contents), &arm_context_addr, 4);
0411 }
0412 
0413 void omap3_control_save_context(void)
0414 {
0415     control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
0416     control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
0417     control_context.mem_dftrw0 =
0418             omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
0419     control_context.mem_dftrw1 =
0420             omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
0421     control_context.msuspendmux_0 =
0422             omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
0423     control_context.msuspendmux_1 =
0424             omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
0425     control_context.msuspendmux_2 =
0426             omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
0427     control_context.msuspendmux_3 =
0428             omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
0429     control_context.msuspendmux_4 =
0430             omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
0431     control_context.msuspendmux_5 =
0432             omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
0433     control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
0434     control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
0435     control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
0436     control_context.iva2_bootaddr =
0437             omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
0438     control_context.iva2_bootmod =
0439             omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
0440     control_context.wkup_ctrl = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL);
0441     control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
0442     control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
0443     control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
0444     control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
0445     control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
0446     control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
0447     control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
0448     control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
0449     control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
0450     control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
0451     control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
0452     control_context.dss_dpll_spreading =
0453             omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
0454     control_context.core_dpll_spreading =
0455             omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
0456     control_context.per_dpll_spreading =
0457             omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
0458     control_context.usbhost_dpll_spreading =
0459         omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
0460     control_context.pbias_lite =
0461             omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
0462     control_context.temp_sensor =
0463             omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
0464     control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
0465     control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
0466     control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
0467     control_context.padconf_sys_nirq =
0468         omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
0469 }
0470 
0471 void omap3_control_restore_context(void)
0472 {
0473     omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
0474     omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
0475     omap_ctrl_writel(control_context.mem_dftrw0,
0476                     OMAP343X_CONTROL_MEM_DFTRW0);
0477     omap_ctrl_writel(control_context.mem_dftrw1,
0478                     OMAP343X_CONTROL_MEM_DFTRW1);
0479     omap_ctrl_writel(control_context.msuspendmux_0,
0480                     OMAP2_CONTROL_MSUSPENDMUX_0);
0481     omap_ctrl_writel(control_context.msuspendmux_1,
0482                     OMAP2_CONTROL_MSUSPENDMUX_1);
0483     omap_ctrl_writel(control_context.msuspendmux_2,
0484                     OMAP2_CONTROL_MSUSPENDMUX_2);
0485     omap_ctrl_writel(control_context.msuspendmux_3,
0486                     OMAP2_CONTROL_MSUSPENDMUX_3);
0487     omap_ctrl_writel(control_context.msuspendmux_4,
0488                     OMAP2_CONTROL_MSUSPENDMUX_4);
0489     omap_ctrl_writel(control_context.msuspendmux_5,
0490                     OMAP2_CONTROL_MSUSPENDMUX_5);
0491     omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
0492     omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
0493     omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
0494     omap_ctrl_writel(control_context.iva2_bootaddr,
0495                     OMAP343X_CONTROL_IVA2_BOOTADDR);
0496     omap_ctrl_writel(control_context.iva2_bootmod,
0497                     OMAP343X_CONTROL_IVA2_BOOTMOD);
0498     omap_ctrl_writel(control_context.wkup_ctrl, OMAP34XX_CONTROL_WKUP_CTRL);
0499     omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
0500     omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
0501     omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
0502     omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
0503     omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
0504     omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
0505     omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
0506     omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
0507     omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
0508     omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
0509     omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
0510     omap_ctrl_writel(control_context.dss_dpll_spreading,
0511                     OMAP343X_CONTROL_DSS_DPLL_SPREADING);
0512     omap_ctrl_writel(control_context.core_dpll_spreading,
0513                     OMAP343X_CONTROL_CORE_DPLL_SPREADING);
0514     omap_ctrl_writel(control_context.per_dpll_spreading,
0515                     OMAP343X_CONTROL_PER_DPLL_SPREADING);
0516     omap_ctrl_writel(control_context.usbhost_dpll_spreading,
0517                 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
0518     omap_ctrl_writel(control_context.pbias_lite,
0519                     OMAP343X_CONTROL_PBIAS_LITE);
0520     omap_ctrl_writel(control_context.temp_sensor,
0521                     OMAP343X_CONTROL_TEMP_SENSOR);
0522     omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
0523     omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
0524     omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
0525     omap_ctrl_writel(control_context.padconf_sys_nirq,
0526              OMAP343X_CONTROL_PADCONF_SYSNIRQ);
0527 }
0528 
0529 void omap3630_ctrl_disable_rta(void)
0530 {
0531     if (!cpu_is_omap3630())
0532         return;
0533     omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
0534 }
0535 
0536 /**
0537  * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
0538  *
0539  * Tell the SCM to start saving the padconf registers, then wait for
0540  * the process to complete.  Returns 0 unconditionally, although it
0541  * should also eventually be able to return -ETIMEDOUT, if the save
0542  * does not complete.
0543  *
0544  * XXX This function is missing a timeout.  What should it be?
0545  */
0546 int omap3_ctrl_save_padconf(void)
0547 {
0548     u32 cpo;
0549 
0550     /* Save the padconf registers */
0551     cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
0552     cpo |= START_PADCONF_SAVE;
0553     omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF);
0554 
0555     /* wait for the save to complete */
0556     while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
0557          & PADCONF_SAVE_DONE))
0558         udelay(1);
0559 
0560     return 0;
0561 }
0562 
0563 /**
0564  * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle
0565  *
0566  * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
0567  * force disable IVA2 so that it does not prevent any low-power states.
0568  */
0569 static void __init omap3_ctrl_set_iva_bootmode_idle(void)
0570 {
0571     omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
0572              OMAP343X_CONTROL_IVA2_BOOTMOD);
0573 }
0574 
0575 /**
0576  * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle
0577  *
0578  * Sets up the pads controlling the stacked modem in such way that the
0579  * device can enter idle.
0580  */
0581 static void __init omap3_ctrl_setup_d2d_padconf(void)
0582 {
0583     u16 mask, padconf;
0584 
0585     /*
0586      * In a stand alone OMAP3430 where there is not a stacked
0587      * modem for the D2D Idle Ack and D2D MStandby must be pulled
0588      * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
0589      * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up.
0590      */
0591     mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
0592     padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
0593     padconf |= mask;
0594     omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
0595 
0596     padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
0597     padconf |= mask;
0598     omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
0599 }
0600 
0601 /**
0602  * omap3_ctrl_init - does static initializations for control module
0603  *
0604  * Initializes system control module. This sets up the sysconfig autoidle,
0605  * and sets up modem and iva2 so that they can be idled properly.
0606  */
0607 void __init omap3_ctrl_init(void)
0608 {
0609     omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
0610 
0611     omap3_ctrl_set_iva_bootmode_idle();
0612 
0613     omap3_ctrl_setup_d2d_padconf();
0614 }
0615 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
0616 
0617 static unsigned long am43xx_control_reg_offsets[] = {
0618     AM33XX_CONTROL_SYSCONFIG_OFFSET,
0619     AM33XX_CONTROL_STATUS_OFFSET,
0620     AM43XX_CONTROL_MPU_L2_CTRL_OFFSET,
0621     AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET,
0622     AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET,
0623     AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET,
0624     AM33XX_CONTROL_BANDGAP_CTRL_OFFSET,
0625     AM33XX_CONTROL_BANDGAP_TRIM_OFFSET,
0626     AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET,
0627     AM33XX_CONTROL_MOSC_CTRL_OFFSET,
0628     AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET,
0629     AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET,
0630     AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET,
0631     AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET,
0632     AM33XX_CONTROL_TPTC_CFG_OFFSET,
0633     AM33XX_CONTROL_USB_CTRL0_OFFSET,
0634     AM33XX_CONTROL_USB_CTRL1_OFFSET,
0635     AM43XX_CONTROL_USB_CTRL2_OFFSET,
0636     AM43XX_CONTROL_GMII_SEL_OFFSET,
0637     AM43XX_CONTROL_MPUSS_CTRL_OFFSET,
0638     AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET,
0639     AM43XX_CONTROL_PWMSS_CTRL_OFFSET,
0640     AM33XX_CONTROL_MREQPRIO_0_OFFSET,
0641     AM33XX_CONTROL_MREQPRIO_1_OFFSET,
0642     AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET,
0643     AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET,
0644     AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET,
0645     AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET,
0646     AM33XX_CONTROL_SMRT_CTRL_OFFSET,
0647     AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET,
0648     AM43XX_CONTROL_CQDETECT_STS_OFFSET,
0649     AM43XX_CONTROL_CQDETECT_STS2_OFFSET,
0650     AM43XX_CONTROL_VTP_CTRL_OFFSET,
0651     AM33XX_CONTROL_VREF_CTRL_OFFSET,
0652     AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET,
0653     AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET,
0654     AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET,
0655     AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET,
0656     AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET,
0657     AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET,
0658     AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET,
0659     AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET,
0660     AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET,
0661     AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET,
0662     AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET,
0663     AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET,
0664     AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET,
0665     AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET,
0666     AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET,
0667     AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET,
0668     AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET,
0669     AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET,
0670     AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET,
0671     AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET,
0672     AM33XX_CONTROL_RESET_ISO_OFFSET,
0673 };
0674 
0675 static u32 am33xx_control_vals[ARRAY_SIZE(am43xx_control_reg_offsets)];
0676 
0677 /**
0678  * am43xx_control_save_context - Save the wakeup domain registers
0679  *
0680  * Save the wkup domain registers
0681  */
0682 static void am43xx_control_save_context(void)
0683 {
0684     int i;
0685 
0686     for (i = 0; i < ARRAY_SIZE(am43xx_control_reg_offsets); i++)
0687         am33xx_control_vals[i] =
0688                 omap_ctrl_readl(am43xx_control_reg_offsets[i]);
0689 }
0690 
0691 /**
0692  * am43xx_control_restore_context - Restore the wakeup domain registers
0693  *
0694  * Restore the wkup domain registers
0695  */
0696 static void am43xx_control_restore_context(void)
0697 {
0698     int i;
0699 
0700     for (i = 0; i < ARRAY_SIZE(am43xx_control_reg_offsets); i++)
0701         omap_ctrl_writel(am33xx_control_vals[i],
0702                  am43xx_control_reg_offsets[i]);
0703 }
0704 
0705 static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
0706 {
0707     switch (cmd) {
0708     case CPU_CLUSTER_PM_ENTER:
0709         if (enable_off_mode)
0710             am43xx_control_save_context();
0711         break;
0712     case CPU_CLUSTER_PM_EXIT:
0713         if (enable_off_mode)
0714             am43xx_control_restore_context();
0715         break;
0716     }
0717 
0718     return NOTIFY_OK;
0719 }
0720 
0721 struct control_init_data {
0722     int index;
0723     void __iomem *mem;
0724     s16 offset;
0725 };
0726 
0727 static struct control_init_data ctrl_data = {
0728     .index = TI_CLKM_CTRL,
0729 };
0730 
0731 static const struct control_init_data omap2_ctrl_data = {
0732     .index = TI_CLKM_CTRL,
0733     .offset = -OMAP2_CONTROL_GENERAL,
0734 };
0735 
0736 static const struct control_init_data ctrl_aux_data = {
0737     .index = TI_CLKM_CTRL_AUX,
0738 };
0739 
0740 static const struct of_device_id omap_scrm_dt_match_table[] = {
0741     { .compatible = "ti,am3-scm", .data = &ctrl_data },
0742     { .compatible = "ti,am4-scm", .data = &ctrl_data },
0743     { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data },
0744     { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data },
0745     { .compatible = "ti,dm814-scm", .data = &ctrl_data },
0746     { .compatible = "ti,dm816-scrm", .data = &ctrl_data },
0747     { .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
0748     { .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
0749     { .compatible = "ti,omap5-scm-wkup-pad-conf", .data = &ctrl_aux_data },
0750     { .compatible = "ti,dra7-scm-core", .data = &ctrl_data },
0751     { }
0752 };
0753 
0754 /**
0755  * omap2_control_base_init - initialize iomappings for the control driver
0756  *
0757  * Detects and initializes the iomappings for the control driver, based
0758  * on the DT data. Returns 0 in success, negative error value
0759  * otherwise.
0760  */
0761 int __init omap2_control_base_init(void)
0762 {
0763     struct device_node *np;
0764     const struct of_device_id *match;
0765     struct control_init_data *data;
0766     void __iomem *mem;
0767 
0768     for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
0769         data = (struct control_init_data *)match->data;
0770 
0771         mem = of_iomap(np, 0);
0772         if (!mem) {
0773             of_node_put(np);
0774             return -ENOMEM;
0775         }
0776 
0777         if (data->index == TI_CLKM_CTRL) {
0778             omap2_ctrl_base = mem;
0779             omap2_ctrl_offset = data->offset;
0780         }
0781 
0782         data->mem = mem;
0783     }
0784 
0785     return 0;
0786 }
0787 
0788 /**
0789  * omap_control_init - low level init for the control driver
0790  *
0791  * Initializes the low level clock infrastructure for control driver.
0792  * Returns 0 in success, negative error value in failure.
0793  */
0794 int __init omap_control_init(void)
0795 {
0796     struct device_node *np, *scm_conf;
0797     const struct of_device_id *match;
0798     const struct omap_prcm_init_data *data;
0799     int ret;
0800     struct regmap *syscon;
0801     static struct notifier_block nb;
0802 
0803     for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
0804         data = match->data;
0805 
0806         /*
0807          * Check if we have scm_conf node, if yes, use this to
0808          * access clock registers.
0809          */
0810         scm_conf = of_get_child_by_name(np, "scm_conf");
0811 
0812         if (scm_conf) {
0813             syscon = syscon_node_to_regmap(scm_conf);
0814 
0815             if (IS_ERR(syscon)) {
0816                 ret = PTR_ERR(syscon);
0817                 goto of_node_put;
0818             }
0819 
0820             if (of_get_child_by_name(scm_conf, "clocks")) {
0821                 ret = omap2_clk_provider_init(scm_conf,
0822                                   data->index,
0823                                   syscon, NULL);
0824                 if (ret)
0825                     goto of_node_put;
0826             }
0827         } else {
0828             /* No scm_conf found, direct access */
0829             ret = omap2_clk_provider_init(np, data->index, NULL,
0830                               data->mem);
0831             if (ret)
0832                 goto of_node_put;
0833         }
0834     }
0835 
0836     /* Only AM43XX can lose ctrl registers context during rtc-ddr suspend */
0837     if (soc_is_am43xx()) {
0838         nb.notifier_call = cpu_notifier;
0839         cpu_pm_register_notifier(&nb);
0840     }
0841 
0842     return 0;
0843 
0844 of_node_put:
0845     of_node_put(np);
0846     return ret;
0847 
0848 }
0849 
0850 /**
0851  * omap3_control_legacy_iomap_init - legacy iomap init for clock providers
0852  *
0853  * Legacy iomap init for clock provider. Needed only by legacy boot mode,
0854  * where the base addresses are not parsed from DT, but still required
0855  * by the clock driver to be setup properly.
0856  */
0857 void __init omap3_control_legacy_iomap_init(void)
0858 {
0859     omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base);
0860 }
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