arm/mach-omap2/cm33xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * AM33XX CM offset macros
0004  *
0005  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
0006  * Vaibhav Hiremath <hvaibhav@ti.com>
0007  */
0008
0009 #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
0010 #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
0011
0012 #include "cm.h"
0013 #include "cm-regbits-33xx.h"
0014 #include "prcm-common.h"
0015
0016 /* CM base address */
0017 #define AM33XX_CM_BASE      0x44e00000
0018
0019 #define AM33XX_CM_REGADDR(inst, reg)                \
0020     AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
0021
0022 /* CM instances */
0023 #define AM33XX_CM_PER_MOD       0x0000
0024 #define AM33XX_CM_WKUP_MOD      0x0400
0025 #define AM33XX_CM_DPLL_MOD      0x0500
0026 #define AM33XX_CM_MPU_MOD       0x0600
0027 #define AM33XX_CM_DEVICE_MOD        0x0700
0028 #define AM33XX_CM_RTC_MOD       0x0800
0029 #define AM33XX_CM_GFX_MOD       0x0900
0030 #define AM33XX_CM_CEFUSE_MOD        0x0A00
0031
0032 /* CM.PER_CM register offsets */
0033 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET     0x0000
0034 #define AM33XX_CM_PER_L4LS_CLKSTCTRL            AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
0035 #define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET      0x0004
0036 #define AM33XX_CM_PER_L3S_CLKSTCTRL         AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
0037 #define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET     0x0008
0038 #define AM33XX_CM_PER_L4FW_CLKSTCTRL            AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
0039 #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET       0x000c
0040 #define AM33XX_CM_PER_L3_CLKSTCTRL          AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
0041 #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET       0x0028
0042 #define AM33XX_CM_PER_EMIF_CLKCTRL          AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
0043 #define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET     0x011c
0044 #define AM33XX_CM_PER_L4HS_CLKSTCTRL            AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
0045 #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET     0x012c
0046 #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL        AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
0047 #define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET        0x0140
0048 #define AM33XX_CM_PER_PRUSS_CLKSTCTRL           AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
0049 #define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET     0x0144
0050 #define AM33XX_CM_PER_CPSW_CLKSTCTRL            AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
0051 #define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET     0x0148
0052 #define AM33XX_CM_PER_LCDC_CLKSTCTRL            AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
0053 #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET    0x0150
0054 #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL       AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
0055
0056 /* CM.WKUP_CM register offsets */
0057 #define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET         0x0000
0058 #define AM33XX_CM_WKUP_CLKSTCTRL            AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
0059 #define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET       0x0018
0060 #define AM33XX_CM_L3_AON_CLKSTCTRL          AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
0061 #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET      0x00cc
0062 #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL         AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
0063
0064 /* CM.DPLL_CM register offsets */
0065 #define AM33XX_CLKSEL_GFX_FCLK              AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
0066
0067 /* CM.MPU_CM register offsets */
0068 #define AM33XX_CM_MPU_CLKSTCTRL_OFFSET          0x0000
0069 #define AM33XX_CM_MPU_CLKSTCTRL             AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
0070 #define AM33XX_CM_MPU_MPU_CLKCTRL           AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
0071
0072 /* CM.DEVICE_CM register offsets */
0073
0074 /* CM.RTC_CM register offsets */
0075 #define AM33XX_CM_RTC_CLKSTCTRL_OFFSET          0x0004
0076 #define AM33XX_CM_RTC_CLKSTCTRL             AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
0077
0078 /* CM.GFX_CM register offsets */
0079 #define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET       0x0000
0080 #define AM33XX_CM_GFX_L3_CLKSTCTRL          AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
0081 #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET  0x000c
0082 #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1     AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
0083
0084 /* CM.CEFUSE_CM register offsets */
0085 #define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET       0x0000
0086 #define AM33XX_CM_CEFUSE_CLKSTCTRL          AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
0087
0088
0089 #ifndef __ASSEMBLER__
0090 int am33xx_cm_init(const struct omap_prcm_init_data *data);
0091 #endif /* ASSEMBLER */
0092 #endif