arm/mach-omap2/cm2xxx_3xxx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * OMAP2/3 Clock Management (CM) register definitions
0004  *
0005  * Copyright (C) 2007-2009 Texas Instruments, Inc.
0006  * Copyright (C) 2007-2010 Nokia Corporation
0007  * Paul Walmsley
0008  *
0009  * The CM hardware modules on the OMAP2/3 are quite similar to each
0010  * other.  The CM modules/instances on OMAP4 are quite different, so
0011  * they are handled in a separate file.
0012  */
0013 #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
0014 #define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
0015
0016 #include "cm.h"
0017
0018 /*
0019  * Module specific CM register offsets from CM_BASE + domain offset
0020  * Use cm_{read,write}_mod_reg() with these registers.
0021  * These register offsets generally appear in more than one PRCM submodule.
0022  */
0023
0024 /* Common between OMAP2 and OMAP3 */
0025
0026 #define CM_FCLKEN                   0x0000
0027 #define CM_FCLKEN1                  CM_FCLKEN
0028 #define CM_CLKEN                    CM_FCLKEN
0029 #define CM_ICLKEN                   0x0010
0030 #define CM_ICLKEN1                  CM_ICLKEN
0031 #define CM_ICLKEN2                  0x0014
0032 #define CM_ICLKEN3                  0x0018
0033 #define CM_IDLEST                   0x0020
0034 #define CM_IDLEST1                  CM_IDLEST
0035 #define CM_IDLEST2                  0x0024
0036 #define OMAP2430_CM_IDLEST3             0x0028
0037 #define CM_AUTOIDLE                 0x0030
0038 #define CM_AUTOIDLE1                    CM_AUTOIDLE
0039 #define CM_AUTOIDLE2                    0x0034
0040 #define CM_AUTOIDLE3                    0x0038
0041 #define CM_CLKSEL                   0x0040
0042 #define CM_CLKSEL1                  CM_CLKSEL
0043 #define CM_CLKSEL2                  0x0044
0044 #define OMAP2_CM_CLKSTCTRL              0x0048
0045
0046 #ifndef __ASSEMBLER__
0047
0048 #include <linux/io.h>
0049
0050 static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
0051 {
0052     return readl_relaxed(cm_base.va + module + idx);
0053 }
0054
0055 static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
0056 {
0057     writel_relaxed(val, cm_base.va + module + idx);
0058 }
0059
0060 /* Read-modify-write a register in a CM module. Caller must lock */
0061 static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
0062                         s16 idx)
0063 {
0064     u32 v;
0065
0066     v = omap2_cm_read_mod_reg(module, idx);
0067     v &= ~mask;
0068     v |= bits;
0069     omap2_cm_write_mod_reg(v, module, idx);
0070
0071     return v;
0072 }
0073
0074 /* Read a CM register, AND it, and shift the result down to bit 0 */
0075 static inline u32 omap2_cm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
0076 {
0077     u32 v;
0078
0079     v = omap2_cm_read_mod_reg(domain, idx);
0080     v &= mask;
0081     v >>= __ffs(mask);
0082
0083     return v;
0084 }
0085
0086 static inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
0087 {
0088     return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
0089 }
0090
0091 static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
0092 {
0093     return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
0094 }
0095
0096 extern int omap2xxx_cm_apll54_enable(void);
0097 extern void omap2xxx_cm_apll54_disable(void);
0098 extern int omap2xxx_cm_apll96_enable(void);
0099 extern void omap2xxx_cm_apll96_disable(void);
0100
0101 #endif
0102
0103 /* CM register bits shared between 24XX and 3430 */
0104
0105 /* CM_CLKSEL_GFX */
0106 #define OMAP_CLKSEL_GFX_SHIFT               0
0107 #define OMAP_CLKSEL_GFX_MASK                (0x7 << 0)
0108 #define OMAP_CLKSEL_GFX_WIDTH               3
0109
0110 /* CM_ICLKEN_GFX */
0111 #define OMAP_EN_GFX_SHIFT               0
0112 #define OMAP_EN_GFX_MASK                (1 << 0)
0113
0114 /* CM_IDLEST_GFX */
0115 #define OMAP_ST_GFX_MASK                (1 << 0)
0116
0117 #endif