arm/mach-omap2/cm2_7xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * DRA7xx CM2 instance offset macros
0004  *
0005  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
0006  *
0007  * Generated by code originally written by:
0008  * Paul Walmsley (paul@pwsan.com)
0009  * Rajendra Nayak (rnayak@ti.com)
0010  * Benoit Cousson (b-cousson@ti.com)
0011  *
0012  * This file is automatically generated from the OMAP hardware databases.
0013  * We respectfully ask that any modifications to this file be coordinated
0014  * with the public linux-omap@vger.kernel.org mailing list and the
0015  * authors above to ensure that the autogeneration scripts are kept
0016  * up-to-date with the file contents.
0017  */
0018
0019 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
0020 #define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
0021
0022 /* CM2 base address */
0023 #define DRA7XX_CM_CORE_BASE     0x4a008000
0024
0025 #define DRA7XX_CM_CORE_REGADDR(inst, reg)               \
0026     OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg))
0027
0028 /* CM_CORE instances */
0029 #define DRA7XX_CM_CORE_OCP_SOCKET_INST  0x0000
0030 #define DRA7XX_CM_CORE_CKGEN_INST   0x0104
0031 #define DRA7XX_CM_CORE_COREAON_INST 0x0600
0032 #define DRA7XX_CM_CORE_CORE_INST    0x0700
0033 #define DRA7XX_CM_CORE_IVA_INST     0x0f00
0034 #define DRA7XX_CM_CORE_CAM_INST     0x1000
0035 #define DRA7XX_CM_CORE_DSS_INST     0x1100
0036 #define DRA7XX_CM_CORE_GPU_INST     0x1200
0037 #define DRA7XX_CM_CORE_L3INIT_INST  0x1300
0038 #define DRA7XX_CM_CORE_CUSTEFUSE_INST   0x1600
0039 #define DRA7XX_CM_CORE_L4PER_INST   0x1700
0040
0041 /* CM_CORE clockdomain register offsets (from instance start) */
0042 #define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS       0x0000
0043 #define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS      0x0000
0044 #define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS         0x0200
0045 #define DRA7XX_CM_CORE_CORE_DMA_CDOFFS          0x0300
0046 #define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS         0x0400
0047 #define DRA7XX_CM_CORE_CORE_ATL_CDOFFS          0x0520
0048 #define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS        0x0600
0049 #define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS      0x0700
0050 #define DRA7XX_CM_CORE_IVA_IVA_CDOFFS           0x0000
0051 #define DRA7XX_CM_CORE_CAM_CAM_CDOFFS           0x0000
0052 #define DRA7XX_CM_CORE_DSS_DSS_CDOFFS           0x0000
0053 #define DRA7XX_CM_CORE_GPU_GPU_CDOFFS           0x0000
0054 #define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS     0x0000
0055 #define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS       0x00a0
0056 #define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS       0x00c0
0057 #define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS   0x0000
0058 #define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS       0x0000
0059 #define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS       0x0180
0060 #define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS      0x01fc
0061 #define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS      0x0210
0062
0063 #endif