arm/mach-omap2/cm2_44xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * OMAP44xx CM2 instance offset macros
0004  *
0005  * Copyright (C) 2009-2011 Texas Instruments, Inc.
0006  * Copyright (C) 2009-2010 Nokia Corporation
0007  *
0008  * Paul Walmsley (paul@pwsan.com)
0009  * Rajendra Nayak (rnayak@ti.com)
0010  * Benoit Cousson (b-cousson@ti.com)
0011  *
0012  * This file is automatically generated from the OMAP hardware databases.
0013  * We respectfully ask that any modifications to this file be coordinated
0014  * with the public linux-omap@vger.kernel.org mailing list and the
0015  * authors above to ensure that the autogeneration scripts are kept
0016  * up-to-date with the file contents.
0017  *
0018  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
0019  *     or "OMAP4430".
0020  */
0021
0022 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
0023 #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
0024
0025 /* CM2 base address */
0026 #define OMAP4430_CM2_BASE       0x4a008000
0027
0028 #define OMAP44XX_CM2_REGADDR(inst, reg)             \
0029     OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg))
0030
0031 /* CM2 instances */
0032 #define OMAP4430_CM2_OCP_SOCKET_INST    0x0000
0033 #define OMAP4430_CM2_CKGEN_INST     0x0100
0034 #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600
0035 #define OMAP4430_CM2_CORE_INST      0x0700
0036 #define OMAP4430_CM2_IVAHD_INST     0x0f00
0037 #define OMAP4430_CM2_CAM_INST       0x1000
0038 #define OMAP4430_CM2_DSS_INST       0x1100
0039 #define OMAP4430_CM2_GFX_INST       0x1200
0040 #define OMAP4430_CM2_L3INIT_INST    0x1300
0041 #define OMAP4430_CM2_L4PER_INST     0x1400
0042 #define OMAP4430_CM2_CEFUSE_INST    0x1600
0043
0044 /* CM2 clockdomain register offsets (from instance start) */
0045 #define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS 0x0000
0046 #define OMAP4430_CM2_CORE_L3_1_CDOFFS       0x0000
0047 #define OMAP4430_CM2_CORE_L3_2_CDOFFS       0x0100
0048 #define OMAP4430_CM2_CORE_DUCATI_CDOFFS     0x0200
0049 #define OMAP4430_CM2_CORE_SDMA_CDOFFS       0x0300
0050 #define OMAP4430_CM2_CORE_MEMIF_CDOFFS      0x0400
0051 #define OMAP4430_CM2_CORE_D2D_CDOFFS        0x0500
0052 #define OMAP4430_CM2_CORE_L4CFG_CDOFFS      0x0600
0053 #define OMAP4430_CM2_CORE_L3INSTR_CDOFFS    0x0700
0054 #define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS     0x0000
0055 #define OMAP4430_CM2_CAM_CAM_CDOFFS     0x0000
0056 #define OMAP4430_CM2_DSS_DSS_CDOFFS     0x0000
0057 #define OMAP4430_CM2_GFX_GFX_CDOFFS     0x0000
0058 #define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS   0x0000
0059 #define OMAP4430_CM2_L4PER_L4PER_CDOFFS     0x0000
0060 #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS     0x0180
0061 #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS   0x0000
0062
0063 #endif