arm/mach-omap2/cm1_7xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * DRA7xx CM1 instance offset macros
0004  *
0005  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
0006  *
0007  * Generated by code originally written by:
0008  * Paul Walmsley (paul@pwsan.com)
0009  * Rajendra Nayak (rnayak@ti.com)
0010  * Benoit Cousson (b-cousson@ti.com)
0011  *
0012  * This file is automatically generated from the OMAP hardware databases.
0013  * We respectfully ask that any modifications to this file be coordinated
0014  * with the public linux-omap@vger.kernel.org mailing list and the
0015  * authors above to ensure that the autogeneration scripts are kept
0016  * up-to-date with the file contents.
0017  */
0018
0019 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
0020 #define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
0021
0022 /* CM1 base address */
0023 #define DRA7XX_CM_CORE_AON_BASE     0x4a005000
0024
0025 #define DRA7XX_CM_CORE_AON_REGADDR(inst, reg)               \
0026     OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))
0027
0028 /* CM_CORE_AON instances */
0029 #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST  0x0000
0030 #define DRA7XX_CM_CORE_AON_CKGEN_INST       0x0100
0031 #define DRA7XX_CM_CORE_AON_MPU_INST     0x0300
0032 #define DRA7XX_CM_CORE_AON_DSP1_INST        0x0400
0033 #define DRA7XX_CM_CORE_AON_IPU_INST     0x0500
0034 #define DRA7XX_CM_CORE_AON_DSP2_INST        0x0600
0035 #define DRA7XX_CM_CORE_AON_EVE1_INST        0x0640
0036 #define DRA7XX_CM_CORE_AON_EVE2_INST        0x0680
0037 #define DRA7XX_CM_CORE_AON_EVE3_INST        0x06c0
0038 #define DRA7XX_CM_CORE_AON_EVE4_INST        0x0700
0039 #define DRA7XX_CM_CORE_AON_RTC_INST     0x0740
0040 #define DRA7XX_CM_CORE_AON_VPE_INST     0x0760
0041
0042 /* CM_CORE_AON clockdomain register offsets (from instance start) */
0043 #define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS   0x0000
0044 #define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS 0x0000
0045 #define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS  0x0000
0046 #define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS   0x0040
0047 #define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS 0x0000
0048 #define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS 0x0000
0049 #define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS 0x0000
0050 #define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS 0x0000
0051 #define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS 0x0000
0052 #define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS   0x0000
0053 #define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS   0x0000
0054
0055 #endif