arm/mach-omap2/cm-regbits-54xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * OMAP54xx Clock Management register bits
0004  *
0005  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
0006  *
0007  * Paul Walmsley (paul@pwsan.com)
0008  * Rajendra Nayak (rnayak@ti.com)
0009  * Benoit Cousson (b-cousson@ti.com)
0010  *
0011  * This file is automatically generated from the OMAP hardware databases.
0012  * We respectfully ask that any modifications to this file be coordinated
0013  * with the public linux-omap@vger.kernel.org mailing list and the
0014  * authors above to ensure that the autogeneration scripts are kept
0015  * up-to-date with the file contents.
0016  */
0017
0018 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
0019 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
0020
0021 #define OMAP54XX_ABE_STATDEP_SHIFT                  3
0022 #define OMAP54XX_AUTO_DPLL_MODE_MASK                    (0x7 << 0)
0023 #define OMAP54XX_CLKSEL_SHIFT                       24
0024 #define OMAP54XX_CLKSEL_WIDTH                       0x1
0025 #define OMAP54XX_CLKSEL_0_0_SHIFT                   0
0026 #define OMAP54XX_CLKSEL_0_0_WIDTH                   0x1
0027 #define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT                 24
0028 #define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH                 0x1
0029 #define OMAP54XX_CLKSEL_DIV_SHIFT                   25
0030 #define OMAP54XX_CLKSEL_DIV_WIDTH                   0x1
0031 #define OMAP54XX_CLKSEL_FCLK_SHIFT                  24
0032 #define OMAP54XX_CLKSEL_FCLK_WIDTH                  0x1
0033 #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT             24
0034 #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH             0x1
0035 #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT              25
0036 #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH              0x1
0037 #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT               26
0038 #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH               0x2
0039 #define OMAP54XX_CLKSEL_OPP_SHIFT                   0
0040 #define OMAP54XX_CLKSEL_OPP_WIDTH                   0x2
0041 #define OMAP54XX_CLKSEL_SOURCE_SHIFT                    24
0042 #define OMAP54XX_CLKSEL_SOURCE_WIDTH                    0x2
0043 #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT            24
0044 #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH            0x1
0045 #define OMAP54XX_CLKSEL_UTMI_P1_SHIFT                   24
0046 #define OMAP54XX_CLKSEL_UTMI_P1_WIDTH                   0x1
0047 #define OMAP54XX_CLKSEL_UTMI_P2_SHIFT                   25
0048 #define OMAP54XX_CLKSEL_UTMI_P2_WIDTH                   0x1
0049 #define OMAP54XX_DIVHS_MASK                     (0x3f << 0)
0050 #define OMAP54XX_DIVHS_0_4_MASK                     (0x1f << 0)
0051 #define OMAP54XX_DIVHS_0_6_MASK                     (0x7f << 0)
0052 #define OMAP54XX_DPLL_DIV_MASK                      (0x7f << 0)
0053 #define OMAP54XX_DPLL_EN_MASK                       (0x7 << 0)
0054 #define OMAP54XX_DPLL_LPMODE_EN_MASK                    (1 << 10)
0055 #define OMAP54XX_DPLL_MULT_MASK                     (0x7ff << 8)
0056 #define OMAP54XX_DPLL_REGM4XEN_MASK                 (1 << 11)
0057 #define OMAP54XX_DPLL_SD_DIV_MASK                   (0xff << 24)
0058 #define OMAP54XX_DSP_STATDEP_SHIFT                  1
0059 #define OMAP54XX_DSS_STATDEP_SHIFT                  8
0060 #define OMAP54XX_EMIF_STATDEP_SHIFT                 4
0061 #define OMAP54XX_GPU_STATDEP_SHIFT                  10
0062 #define OMAP54XX_IPU_STATDEP_SHIFT                  0
0063 #define OMAP54XX_IVA_STATDEP_SHIFT                  2
0064 #define OMAP54XX_L3INIT_STATDEP_SHIFT                   7
0065 #define OMAP54XX_L3MAIN1_STATDEP_SHIFT                  5
0066 #define OMAP54XX_L3MAIN2_STATDEP_SHIFT                  6
0067 #define OMAP54XX_L4CFG_STATDEP_SHIFT                    12
0068 #define OMAP54XX_L4PER_STATDEP_SHIFT                    13
0069 #define OMAP54XX_L4SEC_STATDEP_SHIFT                    14
0070 #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT              11
0071 #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT              8
0072 #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT              9
0073 #define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT                 8
0074 #define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT                8
0075 #define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT                  8
0076 #define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT                 8
0077 #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT            13
0078 #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT            14
0079 #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT            7
0080 #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT             11
0081 #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT             12
0082 #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT             6
0083 #define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT             8
0084 #define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT                8
0085 #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT                11
0086 #define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT                10
0087 #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT              8
0088 #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT               9
0089 #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT                8
0090 #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT                9
0091 #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT                10
0092 #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT                8
0093 #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT                9
0094 #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT                10
0095 #define OMAP54XX_PAD_CLKS_GATE_SHIFT                    8
0096 #define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT                10
0097 #define OMAP54XX_ST_DPLL_CLK_MASK                   (1 << 0)
0098 #define OMAP54XX_SYS_CLKSEL_SHIFT                   0
0099 #define OMAP54XX_SYS_CLKSEL_WIDTH                   0x3
0100 #define OMAP54XX_WKUPAON_STATDEP_SHIFT                  15
0101 #endif