arm/mach-omap2/cm-regbits-34xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
0003 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
0004
0005 /*
0006  * OMAP3430 Clock Management register bits
0007  *
0008  * Copyright (C) 2007-2008 Texas Instruments, Inc.
0009  * Copyright (C) 2007-2008 Nokia Corporation
0010  *
0011  * Written by Paul Walmsley
0012  */
0013
0014 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK        (1 << 0)
0015 #define OMAP3430_ST_IVA2_SHIFT              0
0016 #define OMAP3430_CLKTRCTRL_IVA2_MASK            (0x3 << 0)
0017 #define OMAP3430_CLKACTIVITY_IVA2_MASK          (1 << 0)
0018 #define OMAP3430_CLKTRCTRL_MPU_MASK         (0x3 << 0)
0019 #define OMAP3430_ST_AES2_SHIFT              28
0020 #define OMAP3430_ST_SHA12_SHIFT             27
0021 #define AM35XX_ST_UART4_SHIFT               23
0022 #define OMAP3430_ST_HDQ_SHIFT               22
0023 #define OMAP3430ES2_ST_SSI_IDLE_SHIFT           8
0024 #define OMAP3430_ST_MAILBOXES_SHIFT         7
0025 #define OMAP3430_ST_SAD2D_SHIFT             3
0026 #define OMAP3430_ST_SDMA_SHIFT              2
0027 #define OMAP3430ES2_ST_USBTLL_SHIFT         2
0028 #define OMAP3430ES1_CLKTRCTRL_D2D_MASK          (0x3 << 4)
0029 #define OMAP3430_CLKTRCTRL_L4_MASK          (0x3 << 2)
0030 #define OMAP3430_CLKTRCTRL_L3_MASK          (0x3 << 0)
0031 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK          (0x3 << 0)
0032 #define OMAP3430ES2_CLKTRCTRL_SGX_MASK          (0x3 << 0)
0033 #define OMAP3430_ST_WDT2_SHIFT              5
0034 #define OMAP3430_ST_32KSYNC_SHIFT           2
0035 #define OMAP3430_AUTO_PERIPH_DPLL_MASK          (0x7 << 3)
0036 #define OMAP3430ES2_ST_DSS_IDLE_SHIFT           1
0037 #define OMAP3430_CLKTRCTRL_DSS_MASK         (0x3 << 0)
0038 #define OMAP3430_CLKTRCTRL_CAM_MASK         (0x3 << 0)
0039 #define OMAP3430_ST_MCBSP4_SHIFT            2
0040 #define OMAP3430_ST_MCBSP3_SHIFT            1
0041 #define OMAP3430_ST_MCBSP2_SHIFT            0
0042 #define OMAP3430_CLKTRCTRL_PER_MASK         (0x3 << 0)
0043 #define OMAP3430_CLKTRCTRL_EMU_MASK         (0x3 << 0)
0044 #define OMAP3430_CLKTRCTRL_NEON_MASK            (0x3 << 0)
0045 #define OMAP3430ES2_EN_USBHOST2_SHIFT           1
0046 #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT       1
0047 #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK      (3 << 0)
0048 #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO     0x0
0049 #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP      0x1
0050 #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP     0x2
0051 #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO      0x3
0052 #endif