arm/mach-omap2/cm-regbits-33xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * AM33XX Power Management register bits
0004  *
0005  * This file is automatically generated from the AM33XX hardware databases.
0006  * Vaibhav Hiremath <hvaibhav@ti.com>
0007  *
0008  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
0009  */
0010
0011
0012 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
0013 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
0014
0015 #define AM33XX_CLKOUT2DIV_SHIFT             3
0016 #define AM33XX_CLKOUT2DIV_WIDTH             3
0017 #define AM33XX_CLKOUT2EN_SHIFT              7
0018 #define AM33XX_CLKOUT2SOURCE_MASK           (0x7 << 0)
0019 #define AM33XX_CLKSEL_0_0_SHIFT             0
0020 #define AM33XX_CLKSEL_0_0_WIDTH             1
0021 #define AM33XX_CLKSEL_0_0_MASK              (1 << 0)
0022 #define AM33XX_CLKSEL_0_1_MASK              (3 << 0)
0023 #define AM33XX_CLKSEL_0_2_MASK              (7 << 0)
0024 #define AM33XX_CLKSEL_GFX_FCLK_MASK         (1 << 1)
0025 #define AM33XX_CLKTRCTRL_SHIFT              0
0026 #define AM33XX_CLKTRCTRL_MASK               (0x3 << 0)
0027 #define AM33XX_DPLL_CLKOUT_DIV_SHIFT            0
0028 #define AM33XX_DPLL_CLKOUT_DIV_WIDTH            5
0029 #define AM33XX_DPLL_DIV_MASK                (0x7f << 0)
0030 #define AM33XX_DPLL_PER_DIV_MASK            (0xff << 0)
0031 #define AM33XX_DPLL_EN_MASK             (0x7 << 0)
0032 #define AM33XX_DPLL_MULT_MASK               (0x7ff << 8)
0033 #define AM33XX_DPLL_MULT_PERIPH_MASK            (0xfff << 8)
0034 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT      0
0035 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH      5
0036 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT      0
0037 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH      5
0038 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT      0
0039 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH      5
0040 #define AM33XX_IDLEST_SHIFT             16
0041 #define AM33XX_IDLEST_MASK              (0x3 << 16)
0042 #define AM33XX_MODULEMODE_SHIFT             0
0043 #define AM33XX_MODULEMODE_MASK              (0x3 << 0)
0044 #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT          30
0045 #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT        19
0046 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT     18
0047 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT        18
0048 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT        18
0049 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT        18
0050 #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT          27
0051 #define AM33XX_STM_PMD_CLKDIVSEL_WIDTH          3
0052 #define AM33XX_STM_PMD_CLKSEL_SHIFT         22
0053 #define AM33XX_STM_PMD_CLKSEL_WIDTH         2
0054 #define AM33XX_ST_DPLL_CLK_MASK             (1 << 0)
0055 #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT          8
0056 #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT          24
0057 #define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH          3
0058 #define AM33XX_TRC_PMD_CLKSEL_SHIFT         20
0059 #define AM33XX_TRC_PMD_CLKSEL_WIDTH         2
0060 #endif