arm/mach-omap2/cm-regbits-24xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
0003 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
0004
0005 /*
0006  * OMAP24XX Clock Management register bits
0007  *
0008  * Copyright (C) 2007 Texas Instruments, Inc.
0009  * Copyright (C) 2007 Nokia Corporation
0010  *
0011  * Written by Paul Walmsley
0012  */
0013
0014 #define OMAP24XX_AUTOSTATE_MPU_MASK         (1 << 0)
0015 #define OMAP24XX_EN_DSS1_MASK               (1 << 0)
0016 #define OMAP24XX_ST_MAILBOXES_SHIFT         30
0017 #define OMAP24XX_ST_HDQ_SHIFT               23
0018 #define OMAP2420_ST_I2C2_SHIFT              20
0019 #define OMAP2430_ST_I2CHS1_SHIFT            19
0020 #define OMAP2420_ST_I2C1_SHIFT              19
0021 #define OMAP2430_ST_I2CHS2_SHIFT            20
0022 #define OMAP24XX_ST_MCBSP2_SHIFT            16
0023 #define OMAP24XX_ST_MCBSP1_SHIFT            15
0024 #define OMAP2430_ST_MCBSP5_SHIFT            5
0025 #define OMAP2430_ST_MCBSP4_SHIFT            4
0026 #define OMAP2430_ST_MCBSP3_SHIFT            3
0027 #define OMAP24XX_ST_AES_SHIFT               3
0028 #define OMAP24XX_ST_RNG_SHIFT               2
0029 #define OMAP24XX_ST_SHA_SHIFT               1
0030 #define OMAP24XX_CLKSEL_DSS2_MASK           (0x1 << 13)
0031 #define OMAP24XX_AUTOSTATE_DSS_MASK         (1 << 2)
0032 #define OMAP24XX_AUTOSTATE_L4_MASK          (1 << 1)
0033 #define OMAP24XX_AUTOSTATE_L3_MASK          (1 << 0)
0034 #define OMAP24XX_AUTOSTATE_GFX_MASK         (1 << 0)
0035 #define OMAP24XX_ST_MPU_WDT_SHIFT           3
0036 #define OMAP24XX_ST_32KSYNC_SHIFT           1
0037 #define OMAP24XX_EN_54M_PLL_SHIFT           6
0038 #define OMAP24XX_EN_96M_PLL_SHIFT           2
0039 #define OMAP24XX_ST_54M_APLL_SHIFT          9
0040 #define OMAP24XX_ST_96M_APLL_SHIFT          8
0041 #define OMAP24XX_AUTO_54M_MASK              (0x3 << 6)
0042 #define OMAP24XX_AUTO_96M_MASK              (0x3 << 2)
0043 #define OMAP24XX_AUTO_DPLL_SHIFT            0
0044 #define OMAP24XX_AUTO_DPLL_MASK             (0x3 << 0)
0045 #define OMAP24XX_CORE_CLK_SRC_MASK          (0x3 << 0)
0046 #define OMAP2420_AUTOSTATE_IVA_MASK         (1 << 8)
0047 #define OMAP24XX_AUTOSTATE_DSP_MASK         (1 << 0)
0048 #define OMAP2430_AUTOSTATE_MDM_MASK         (1 << 0)
0049 #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO     0x0
0050 #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO      0x1
0051 #endif