arm/mach-omap2/clockdomains81xx_data.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * TI81XX Clock Domain data.
0004  *
0005  * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
0006  * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
0007  */
0008
0009 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
0010 #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
0011
0012 #include <linux/kernel.h>
0013 #include <linux/io.h>
0014
0015 #include "clockdomain.h"
0016 #include "cm81xx.h"
0017
0018 /*
0019  * Note that 814x seems to have HWSUP_SWSUP for many clockdomains
0020  * while 816x does not. According to the TRM, 816x only has HWSUP
0021  * for ALWON_L3_FAST. Also note that the TI tree clockdomains81xx.h
0022  * seems to have the related ifdef the wrong way around claiming
0023  * 816x supports HWSUP while 814x does not. For now, we only set
0024  * HWSUP for ALWON_L3_FAST as that seems to be supported for both
0025  * dm814x and dm816x.
0026  */
0027
0028 /* Common for 81xx */
0029
0030 static struct clockdomain alwon_l3_slow_81xx_clkdm = {
0031     .name       = "alwon_l3s_clkdm",
0032     .pwrdm      = { .name = "alwon_pwrdm" },
0033     .cm_inst    = TI81XX_CM_ALWON_MOD,
0034     .clkdm_offs = TI81XX_CM_ALWON_L3_SLOW_CLKDM,
0035     .flags      = CLKDM_CAN_SWSUP,
0036 };
0037
0038 static struct clockdomain alwon_l3_med_81xx_clkdm = {
0039     .name       = "alwon_l3_med_clkdm",
0040     .pwrdm      = { .name = "alwon_pwrdm" },
0041     .cm_inst    = TI81XX_CM_ALWON_MOD,
0042     .clkdm_offs = TI81XX_CM_ALWON_L3_MED_CLKDM,
0043     .flags      = CLKDM_CAN_SWSUP,
0044 };
0045
0046 static struct clockdomain alwon_l3_fast_81xx_clkdm = {
0047     .name       = "alwon_l3_fast_clkdm",
0048     .pwrdm      = { .name = "alwon_pwrdm" },
0049     .cm_inst    = TI81XX_CM_ALWON_MOD,
0050     .clkdm_offs = TI81XX_CM_ALWON_L3_FAST_CLKDM,
0051     .flags      = CLKDM_CAN_HWSUP_SWSUP,
0052 };
0053
0054 static struct clockdomain alwon_ethernet_81xx_clkdm = {
0055     .name       = "alwon_ethernet_clkdm",
0056     .pwrdm      = { .name = "alwon_pwrdm" },
0057     .cm_inst    = TI81XX_CM_ALWON_MOD,
0058     .clkdm_offs = TI81XX_CM_ETHERNET_CLKDM,
0059     .flags      = CLKDM_CAN_SWSUP,
0060 };
0061
0062 static struct clockdomain mmu_81xx_clkdm = {
0063     .name       = "mmu_clkdm",
0064     .pwrdm      = { .name = "alwon_pwrdm" },
0065     .cm_inst    = TI81XX_CM_ALWON_MOD,
0066     .clkdm_offs = TI81XX_CM_MMU_CLKDM,
0067     .flags      = CLKDM_CAN_SWSUP,
0068 };
0069
0070 static struct clockdomain mmu_cfg_81xx_clkdm = {
0071     .name       = "mmu_cfg_clkdm",
0072     .pwrdm      = { .name = "alwon_pwrdm" },
0073     .cm_inst    = TI81XX_CM_ALWON_MOD,
0074     .clkdm_offs = TI81XX_CM_MMUCFG_CLKDM,
0075     .flags      = CLKDM_CAN_SWSUP,
0076 };
0077
0078 static struct clockdomain default_l3_slow_81xx_clkdm = {
0079     .name       = "default_l3_slow_clkdm",
0080     .pwrdm      = { .name = "default_pwrdm" },
0081     .cm_inst    = TI81XX_CM_DEFAULT_MOD,
0082     .clkdm_offs = TI816X_CM_DEFAULT_L3_SLOW_CLKDM,
0083     .flags      = CLKDM_CAN_SWSUP,
0084 };
0085
0086 static struct clockdomain default_sata_81xx_clkdm = {
0087     .name       = "default_clkdm",
0088     .pwrdm      = { .name = "default_pwrdm" },
0089     .cm_inst    = TI81XX_CM_DEFAULT_MOD,
0090     .clkdm_offs = TI816X_CM_DEFAULT_SATA_CLKDM,
0091     .flags      = CLKDM_CAN_SWSUP,
0092 };
0093
0094 /* 816x only */
0095
0096 static struct clockdomain alwon_mpu_816x_clkdm = {
0097     .name       = "alwon_mpu_clkdm",
0098     .pwrdm      = { .name = "alwon_pwrdm" },
0099     .cm_inst    = TI81XX_CM_ALWON_MOD,
0100     .clkdm_offs = TI81XX_CM_ALWON_MPU_CLKDM,
0101     .flags      = CLKDM_CAN_SWSUP,
0102 };
0103
0104 static struct clockdomain active_gem_816x_clkdm = {
0105     .name       = "active_gem_clkdm",
0106     .pwrdm      = { .name = "active_pwrdm" },
0107     .cm_inst    = TI81XX_CM_ACTIVE_MOD,
0108     .clkdm_offs = TI816X_CM_ACTIVE_GEM_CLKDM,
0109     .flags      = CLKDM_CAN_SWSUP,
0110 };
0111
0112 static struct clockdomain ivahd0_816x_clkdm = {
0113     .name       = "ivahd0_clkdm",
0114     .pwrdm      = { .name = "ivahd0_pwrdm" },
0115     .cm_inst    = TI816X_CM_IVAHD0_MOD,
0116     .clkdm_offs = TI816X_CM_IVAHD0_CLKDM,
0117     .flags      = CLKDM_CAN_SWSUP,
0118 };
0119
0120 static struct clockdomain ivahd1_816x_clkdm = {
0121     .name       = "ivahd1_clkdm",
0122     .pwrdm      = { .name = "ivahd1_pwrdm" },
0123     .cm_inst    = TI816X_CM_IVAHD1_MOD,
0124     .clkdm_offs = TI816X_CM_IVAHD1_CLKDM,
0125     .flags      = CLKDM_CAN_SWSUP,
0126 };
0127
0128 static struct clockdomain ivahd2_816x_clkdm = {
0129     .name       = "ivahd2_clkdm",
0130     .pwrdm      = { .name = "ivahd2_pwrdm" },
0131     .cm_inst    = TI816X_CM_IVAHD2_MOD,
0132     .clkdm_offs = TI816X_CM_IVAHD2_CLKDM,
0133     .flags      = CLKDM_CAN_SWSUP,
0134 };
0135
0136 static struct clockdomain sgx_816x_clkdm = {
0137     .name       = "sgx_clkdm",
0138     .pwrdm      = { .name = "sgx_pwrdm" },
0139     .cm_inst    = TI81XX_CM_SGX_MOD,
0140     .clkdm_offs = TI816X_CM_SGX_CLKDM,
0141     .flags      = CLKDM_CAN_SWSUP,
0142 };
0143
0144 static struct clockdomain default_l3_med_816x_clkdm = {
0145     .name       = "default_l3_med_clkdm",
0146     .pwrdm      = { .name = "default_pwrdm" },
0147     .cm_inst    = TI81XX_CM_DEFAULT_MOD,
0148     .clkdm_offs = TI816X_CM_DEFAULT_L3_MED_CLKDM,
0149     .flags      = CLKDM_CAN_SWSUP,
0150 };
0151
0152 static struct clockdomain default_ducati_816x_clkdm = {
0153     .name       = "default_ducati_clkdm",
0154     .pwrdm      = { .name = "default_pwrdm" },
0155     .cm_inst    = TI81XX_CM_DEFAULT_MOD,
0156     .clkdm_offs = TI816X_CM_DEFAULT_DUCATI_CLKDM,
0157     .flags      = CLKDM_CAN_SWSUP,
0158 };
0159
0160 static struct clockdomain default_pci_816x_clkdm = {
0161     .name       = "default_pci_clkdm",
0162     .pwrdm      = { .name = "default_pwrdm" },
0163     .cm_inst    = TI81XX_CM_DEFAULT_MOD,
0164     .clkdm_offs = TI816X_CM_DEFAULT_PCI_CLKDM,
0165     .flags      = CLKDM_CAN_SWSUP,
0166 };
0167
0168 static struct clockdomain *clockdomains_ti814x[] __initdata = {
0169     &alwon_l3_slow_81xx_clkdm,
0170     &alwon_l3_med_81xx_clkdm,
0171     &alwon_l3_fast_81xx_clkdm,
0172     &alwon_ethernet_81xx_clkdm,
0173     &mmu_81xx_clkdm,
0174     &mmu_cfg_81xx_clkdm,
0175     &default_l3_slow_81xx_clkdm,
0176     &default_sata_81xx_clkdm,
0177     NULL,
0178 };
0179
0180 void __init ti814x_clockdomains_init(void)
0181 {
0182     clkdm_register_platform_funcs(&am33xx_clkdm_operations);
0183     clkdm_register_clkdms(clockdomains_ti814x);
0184     clkdm_complete_init();
0185 }
0186
0187 static struct clockdomain *clockdomains_ti816x[] __initdata = {
0188     &alwon_mpu_816x_clkdm,
0189     &alwon_l3_slow_81xx_clkdm,
0190     &alwon_l3_med_81xx_clkdm,
0191     &alwon_l3_fast_81xx_clkdm,
0192     &alwon_ethernet_81xx_clkdm,
0193     &mmu_81xx_clkdm,
0194     &mmu_cfg_81xx_clkdm,
0195     &active_gem_816x_clkdm,
0196     &ivahd0_816x_clkdm,
0197     &ivahd1_816x_clkdm,
0198     &ivahd2_816x_clkdm,
0199     &sgx_816x_clkdm,
0200     &default_l3_med_816x_clkdm,
0201     &default_ducati_816x_clkdm,
0202     &default_pci_816x_clkdm,
0203     &default_l3_slow_81xx_clkdm,
0204     &default_sata_81xx_clkdm,
0205     NULL,
0206 };
0207
0208 void __init ti816x_clockdomains_init(void)
0209 {
0210     clkdm_register_platform_funcs(&am33xx_clkdm_operations);
0211     clkdm_register_clkdms(clockdomains_ti816x);
0212     clkdm_complete_init();
0213 }
0214 #endif