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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * DRA7xx Clock domains framework
0004  *
0005  * Copyright (C) 2009-2013 Texas Instruments, Inc.
0006  * Copyright (C) 2009-2011 Nokia Corporation
0007  *
0008  * Generated by code originally written by:
0009  * Abhijit Pagare (abhijitpagare@ti.com)
0010  * Benoit Cousson (b-cousson@ti.com)
0011  * Paul Walmsley (paul@pwsan.com)
0012  *
0013  * This file is automatically generated from the OMAP hardware databases.
0014  * We respectfully ask that any modifications to this file be coordinated
0015  * with the public linux-omap@vger.kernel.org mailing list and the
0016  * authors above to ensure that the autogeneration scripts are kept
0017  * up-to-date with the file contents.
0018  */
0019 
0020 #include <linux/kernel.h>
0021 #include <linux/io.h>
0022 
0023 #include "clockdomain.h"
0024 #include "cm1_7xx.h"
0025 #include "cm2_7xx.h"
0026 
0027 #include "cm-regbits-7xx.h"
0028 #include "prm7xx.h"
0029 #include "prcm44xx.h"
0030 #include "prcm_mpu7xx.h"
0031 
0032 /* Static Dependencies for DRA7xx Clock Domains */
0033 
0034 static struct clkdm_dep cam_wkup_sleep_deps[] = {
0035     { .clkdm_name = "emif_clkdm" },
0036     { NULL },
0037 };
0038 
0039 static struct clkdm_dep dma_wkup_sleep_deps[] = {
0040     { .clkdm_name = "dss_clkdm" },
0041     { .clkdm_name = "emif_clkdm" },
0042     { .clkdm_name = "ipu_clkdm" },
0043     { .clkdm_name = "ipu1_clkdm" },
0044     { .clkdm_name = "ipu2_clkdm" },
0045     { .clkdm_name = "iva_clkdm" },
0046     { .clkdm_name = "l3init_clkdm" },
0047     { .clkdm_name = "l4cfg_clkdm" },
0048     { .clkdm_name = "l4per_clkdm" },
0049     { .clkdm_name = "l4per2_clkdm" },
0050     { .clkdm_name = "l4per3_clkdm" },
0051     { .clkdm_name = "l4sec_clkdm" },
0052     { .clkdm_name = "pcie_clkdm" },
0053     { .clkdm_name = "wkupaon_clkdm" },
0054     { NULL },
0055 };
0056 
0057 static struct clkdm_dep dsp1_wkup_sleep_deps[] = {
0058     { .clkdm_name = "atl_clkdm" },
0059     { .clkdm_name = "cam_clkdm" },
0060     { .clkdm_name = "dsp2_clkdm" },
0061     { .clkdm_name = "dss_clkdm" },
0062     { .clkdm_name = "emif_clkdm" },
0063     { .clkdm_name = "eve1_clkdm" },
0064     { .clkdm_name = "eve2_clkdm" },
0065     { .clkdm_name = "eve3_clkdm" },
0066     { .clkdm_name = "eve4_clkdm" },
0067     { .clkdm_name = "gmac_clkdm" },
0068     { .clkdm_name = "gpu_clkdm" },
0069     { .clkdm_name = "ipu_clkdm" },
0070     { .clkdm_name = "ipu1_clkdm" },
0071     { .clkdm_name = "ipu2_clkdm" },
0072     { .clkdm_name = "iva_clkdm" },
0073     { .clkdm_name = "l3init_clkdm" },
0074     { .clkdm_name = "l4per_clkdm" },
0075     { .clkdm_name = "l4per2_clkdm" },
0076     { .clkdm_name = "l4per3_clkdm" },
0077     { .clkdm_name = "l4sec_clkdm" },
0078     { .clkdm_name = "pcie_clkdm" },
0079     { .clkdm_name = "vpe_clkdm" },
0080     { .clkdm_name = "wkupaon_clkdm" },
0081     { NULL },
0082 };
0083 
0084 static struct clkdm_dep dsp2_wkup_sleep_deps[] = {
0085     { .clkdm_name = "atl_clkdm" },
0086     { .clkdm_name = "cam_clkdm" },
0087     { .clkdm_name = "dsp1_clkdm" },
0088     { .clkdm_name = "dss_clkdm" },
0089     { .clkdm_name = "emif_clkdm" },
0090     { .clkdm_name = "eve1_clkdm" },
0091     { .clkdm_name = "eve2_clkdm" },
0092     { .clkdm_name = "eve3_clkdm" },
0093     { .clkdm_name = "eve4_clkdm" },
0094     { .clkdm_name = "gmac_clkdm" },
0095     { .clkdm_name = "gpu_clkdm" },
0096     { .clkdm_name = "ipu_clkdm" },
0097     { .clkdm_name = "ipu1_clkdm" },
0098     { .clkdm_name = "ipu2_clkdm" },
0099     { .clkdm_name = "iva_clkdm" },
0100     { .clkdm_name = "l3init_clkdm" },
0101     { .clkdm_name = "l4per_clkdm" },
0102     { .clkdm_name = "l4per2_clkdm" },
0103     { .clkdm_name = "l4per3_clkdm" },
0104     { .clkdm_name = "l4sec_clkdm" },
0105     { .clkdm_name = "pcie_clkdm" },
0106     { .clkdm_name = "vpe_clkdm" },
0107     { .clkdm_name = "wkupaon_clkdm" },
0108     { NULL },
0109 };
0110 
0111 static struct clkdm_dep dss_wkup_sleep_deps[] = {
0112     { .clkdm_name = "emif_clkdm" },
0113     { .clkdm_name = "iva_clkdm" },
0114     { NULL },
0115 };
0116 
0117 static struct clkdm_dep eve1_wkup_sleep_deps[] = {
0118     { .clkdm_name = "emif_clkdm" },
0119     { .clkdm_name = "eve2_clkdm" },
0120     { .clkdm_name = "eve3_clkdm" },
0121     { .clkdm_name = "eve4_clkdm" },
0122     { .clkdm_name = "iva_clkdm" },
0123     { NULL },
0124 };
0125 
0126 static struct clkdm_dep eve2_wkup_sleep_deps[] = {
0127     { .clkdm_name = "emif_clkdm" },
0128     { .clkdm_name = "eve1_clkdm" },
0129     { .clkdm_name = "eve3_clkdm" },
0130     { .clkdm_name = "eve4_clkdm" },
0131     { .clkdm_name = "iva_clkdm" },
0132     { NULL },
0133 };
0134 
0135 static struct clkdm_dep eve3_wkup_sleep_deps[] = {
0136     { .clkdm_name = "emif_clkdm" },
0137     { .clkdm_name = "eve1_clkdm" },
0138     { .clkdm_name = "eve2_clkdm" },
0139     { .clkdm_name = "eve4_clkdm" },
0140     { .clkdm_name = "iva_clkdm" },
0141     { NULL },
0142 };
0143 
0144 static struct clkdm_dep eve4_wkup_sleep_deps[] = {
0145     { .clkdm_name = "emif_clkdm" },
0146     { .clkdm_name = "eve1_clkdm" },
0147     { .clkdm_name = "eve2_clkdm" },
0148     { .clkdm_name = "eve3_clkdm" },
0149     { .clkdm_name = "iva_clkdm" },
0150     { NULL },
0151 };
0152 
0153 static struct clkdm_dep gmac_wkup_sleep_deps[] = {
0154     { .clkdm_name = "emif_clkdm" },
0155     { .clkdm_name = "l4per2_clkdm" },
0156     { NULL },
0157 };
0158 
0159 static struct clkdm_dep gpu_wkup_sleep_deps[] = {
0160     { .clkdm_name = "emif_clkdm" },
0161     { .clkdm_name = "iva_clkdm" },
0162     { NULL },
0163 };
0164 
0165 static struct clkdm_dep ipu1_wkup_sleep_deps[] = {
0166     { .clkdm_name = "atl_clkdm" },
0167     { .clkdm_name = "dsp1_clkdm" },
0168     { .clkdm_name = "dsp2_clkdm" },
0169     { .clkdm_name = "dss_clkdm" },
0170     { .clkdm_name = "emif_clkdm" },
0171     { .clkdm_name = "eve1_clkdm" },
0172     { .clkdm_name = "eve2_clkdm" },
0173     { .clkdm_name = "eve3_clkdm" },
0174     { .clkdm_name = "eve4_clkdm" },
0175     { .clkdm_name = "gmac_clkdm" },
0176     { .clkdm_name = "gpu_clkdm" },
0177     { .clkdm_name = "ipu_clkdm" },
0178     { .clkdm_name = "ipu2_clkdm" },
0179     { .clkdm_name = "iva_clkdm" },
0180     { .clkdm_name = "l3init_clkdm" },
0181     { .clkdm_name = "l3main1_clkdm" },
0182     { .clkdm_name = "l4cfg_clkdm" },
0183     { .clkdm_name = "l4per_clkdm" },
0184     { .clkdm_name = "l4per2_clkdm" },
0185     { .clkdm_name = "l4per3_clkdm" },
0186     { .clkdm_name = "l4sec_clkdm" },
0187     { .clkdm_name = "pcie_clkdm" },
0188     { .clkdm_name = "vpe_clkdm" },
0189     { .clkdm_name = "wkupaon_clkdm" },
0190     { NULL },
0191 };
0192 
0193 static struct clkdm_dep ipu2_wkup_sleep_deps[] = {
0194     { .clkdm_name = "atl_clkdm" },
0195     { .clkdm_name = "dsp1_clkdm" },
0196     { .clkdm_name = "dsp2_clkdm" },
0197     { .clkdm_name = "dss_clkdm" },
0198     { .clkdm_name = "emif_clkdm" },
0199     { .clkdm_name = "eve1_clkdm" },
0200     { .clkdm_name = "eve2_clkdm" },
0201     { .clkdm_name = "eve3_clkdm" },
0202     { .clkdm_name = "eve4_clkdm" },
0203     { .clkdm_name = "gmac_clkdm" },
0204     { .clkdm_name = "gpu_clkdm" },
0205     { .clkdm_name = "ipu_clkdm" },
0206     { .clkdm_name = "ipu1_clkdm" },
0207     { .clkdm_name = "iva_clkdm" },
0208     { .clkdm_name = "l3init_clkdm" },
0209     { .clkdm_name = "l3main1_clkdm" },
0210     { .clkdm_name = "l4cfg_clkdm" },
0211     { .clkdm_name = "l4per_clkdm" },
0212     { .clkdm_name = "l4per2_clkdm" },
0213     { .clkdm_name = "l4per3_clkdm" },
0214     { .clkdm_name = "l4sec_clkdm" },
0215     { .clkdm_name = "pcie_clkdm" },
0216     { .clkdm_name = "vpe_clkdm" },
0217     { .clkdm_name = "wkupaon_clkdm" },
0218     { NULL },
0219 };
0220 
0221 static struct clkdm_dep iva_wkup_sleep_deps[] = {
0222     { .clkdm_name = "emif_clkdm" },
0223     { NULL },
0224 };
0225 
0226 static struct clkdm_dep l3init_wkup_sleep_deps[] = {
0227     { .clkdm_name = "emif_clkdm" },
0228     { .clkdm_name = "iva_clkdm" },
0229     { .clkdm_name = "l4cfg_clkdm" },
0230     { .clkdm_name = "l4per_clkdm" },
0231     { .clkdm_name = "l4per3_clkdm" },
0232     { .clkdm_name = "l4sec_clkdm" },
0233     { .clkdm_name = "wkupaon_clkdm" },
0234     { NULL },
0235 };
0236 
0237 static struct clkdm_dep l4per2_wkup_sleep_deps[] = {
0238     { .clkdm_name = "dsp1_clkdm" },
0239     { .clkdm_name = "dsp2_clkdm" },
0240     { .clkdm_name = "ipu1_clkdm" },
0241     { .clkdm_name = "ipu2_clkdm" },
0242     { NULL },
0243 };
0244 
0245 static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
0246     { .clkdm_name = "emif_clkdm" },
0247     { .clkdm_name = "l4per_clkdm" },
0248     { NULL },
0249 };
0250 
0251 static struct clkdm_dep mpu_wkup_sleep_deps[] = {
0252     { .clkdm_name = "cam_clkdm" },
0253     { .clkdm_name = "dsp1_clkdm" },
0254     { .clkdm_name = "dsp2_clkdm" },
0255     { .clkdm_name = "dss_clkdm" },
0256     { .clkdm_name = "emif_clkdm" },
0257     { .clkdm_name = "eve1_clkdm" },
0258     { .clkdm_name = "eve2_clkdm" },
0259     { .clkdm_name = "eve3_clkdm" },
0260     { .clkdm_name = "eve4_clkdm" },
0261     { .clkdm_name = "gmac_clkdm" },
0262     { .clkdm_name = "gpu_clkdm" },
0263     { .clkdm_name = "ipu_clkdm" },
0264     { .clkdm_name = "ipu1_clkdm" },
0265     { .clkdm_name = "ipu2_clkdm" },
0266     { .clkdm_name = "iva_clkdm" },
0267     { .clkdm_name = "l3init_clkdm" },
0268     { .clkdm_name = "l3main1_clkdm" },
0269     { .clkdm_name = "l4cfg_clkdm" },
0270     { .clkdm_name = "l4per_clkdm" },
0271     { .clkdm_name = "l4per2_clkdm" },
0272     { .clkdm_name = "l4per3_clkdm" },
0273     { .clkdm_name = "l4sec_clkdm" },
0274     { .clkdm_name = "pcie_clkdm" },
0275     { .clkdm_name = "vpe_clkdm" },
0276     { .clkdm_name = "wkupaon_clkdm" },
0277     { NULL },
0278 };
0279 
0280 static struct clkdm_dep pcie_wkup_sleep_deps[] = {
0281     { .clkdm_name = "atl_clkdm" },
0282     { .clkdm_name = "cam_clkdm" },
0283     { .clkdm_name = "dsp1_clkdm" },
0284     { .clkdm_name = "dsp2_clkdm" },
0285     { .clkdm_name = "dss_clkdm" },
0286     { .clkdm_name = "emif_clkdm" },
0287     { .clkdm_name = "eve1_clkdm" },
0288     { .clkdm_name = "eve2_clkdm" },
0289     { .clkdm_name = "eve3_clkdm" },
0290     { .clkdm_name = "eve4_clkdm" },
0291     { .clkdm_name = "gmac_clkdm" },
0292     { .clkdm_name = "gpu_clkdm" },
0293     { .clkdm_name = "ipu_clkdm" },
0294     { .clkdm_name = "ipu1_clkdm" },
0295     { .clkdm_name = "iva_clkdm" },
0296     { .clkdm_name = "l3init_clkdm" },
0297     { .clkdm_name = "l4cfg_clkdm" },
0298     { .clkdm_name = "l4per_clkdm" },
0299     { .clkdm_name = "l4per2_clkdm" },
0300     { .clkdm_name = "l4per3_clkdm" },
0301     { .clkdm_name = "l4sec_clkdm" },
0302     { .clkdm_name = "vpe_clkdm" },
0303     { NULL },
0304 };
0305 
0306 static struct clkdm_dep vpe_wkup_sleep_deps[] = {
0307     { .clkdm_name = "emif_clkdm" },
0308     { .clkdm_name = "l4per3_clkdm" },
0309     { NULL },
0310 };
0311 
0312 static struct clockdomain l4per3_7xx_clkdm = {
0313     .name         = "l4per3_clkdm",
0314     .pwrdm        = { .name = "l4per_pwrdm" },
0315     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0316     .cm_inst      = DRA7XX_CM_CORE_L4PER_INST,
0317     .clkdm_offs   = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS,
0318     .dep_bit      = DRA7XX_L4PER3_STATDEP_SHIFT,
0319     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0320 };
0321 
0322 static struct clockdomain l4per2_7xx_clkdm = {
0323     .name         = "l4per2_clkdm",
0324     .pwrdm        = { .name = "l4per_pwrdm" },
0325     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0326     .cm_inst      = DRA7XX_CM_CORE_L4PER_INST,
0327     .clkdm_offs   = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS,
0328     .dep_bit      = DRA7XX_L4PER2_STATDEP_SHIFT,
0329     .wkdep_srcs   = l4per2_wkup_sleep_deps,
0330     .sleepdep_srcs    = l4per2_wkup_sleep_deps,
0331     .flags        = CLKDM_CAN_SWSUP,
0332 };
0333 
0334 static struct clockdomain mpu0_7xx_clkdm = {
0335     .name         = "mpu0_clkdm",
0336     .pwrdm        = { .name = "cpu0_pwrdm" },
0337     .prcm_partition   = DRA7XX_MPU_PRCM_PARTITION,
0338     .cm_inst      = DRA7XX_MPU_PRCM_CM_C0_INST,
0339     .clkdm_offs   = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS,
0340     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0341 };
0342 
0343 static struct clockdomain iva_7xx_clkdm = {
0344     .name         = "iva_clkdm",
0345     .pwrdm        = { .name = "iva_pwrdm" },
0346     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0347     .cm_inst      = DRA7XX_CM_CORE_IVA_INST,
0348     .clkdm_offs   = DRA7XX_CM_CORE_IVA_IVA_CDOFFS,
0349     .dep_bit      = DRA7XX_IVA_STATDEP_SHIFT,
0350     .wkdep_srcs   = iva_wkup_sleep_deps,
0351     .sleepdep_srcs    = iva_wkup_sleep_deps,
0352     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0353 };
0354 
0355 static struct clockdomain coreaon_7xx_clkdm = {
0356     .name         = "coreaon_clkdm",
0357     .pwrdm        = { .name = "coreaon_pwrdm" },
0358     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0359     .cm_inst      = DRA7XX_CM_CORE_COREAON_INST,
0360     .clkdm_offs   = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS,
0361     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0362 };
0363 
0364 static struct clockdomain ipu1_7xx_clkdm = {
0365     .name         = "ipu1_clkdm",
0366     .pwrdm        = { .name = "ipu_pwrdm" },
0367     .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
0368     .cm_inst      = DRA7XX_CM_CORE_AON_IPU_INST,
0369     .clkdm_offs   = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS,
0370     .dep_bit      = DRA7XX_IPU1_STATDEP_SHIFT,
0371     .wkdep_srcs   = ipu1_wkup_sleep_deps,
0372     .sleepdep_srcs    = ipu1_wkup_sleep_deps,
0373     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0374 };
0375 
0376 static struct clockdomain ipu2_7xx_clkdm = {
0377     .name         = "ipu2_clkdm",
0378     .pwrdm        = { .name = "core_pwrdm" },
0379     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0380     .cm_inst      = DRA7XX_CM_CORE_CORE_INST,
0381     .clkdm_offs   = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS,
0382     .dep_bit      = DRA7XX_IPU2_STATDEP_SHIFT,
0383     .wkdep_srcs   = ipu2_wkup_sleep_deps,
0384     .sleepdep_srcs    = ipu2_wkup_sleep_deps,
0385     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0386 };
0387 
0388 static struct clockdomain l3init_7xx_clkdm = {
0389     .name         = "l3init_clkdm",
0390     .pwrdm        = { .name = "l3init_pwrdm" },
0391     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0392     .cm_inst      = DRA7XX_CM_CORE_L3INIT_INST,
0393     .clkdm_offs   = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
0394     .dep_bit      = DRA7XX_L3INIT_STATDEP_SHIFT,
0395     .wkdep_srcs   = l3init_wkup_sleep_deps,
0396     .sleepdep_srcs    = l3init_wkup_sleep_deps,
0397     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0398 };
0399 
0400 static struct clockdomain l4sec_7xx_clkdm = {
0401     .name         = "l4sec_clkdm",
0402     .pwrdm        = { .name = "l4per_pwrdm" },
0403     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0404     .cm_inst      = DRA7XX_CM_CORE_L4PER_INST,
0405     .clkdm_offs   = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS,
0406     .dep_bit      = DRA7XX_L4SEC_STATDEP_SHIFT,
0407     .wkdep_srcs   = l4sec_wkup_sleep_deps,
0408     .sleepdep_srcs    = l4sec_wkup_sleep_deps,
0409     .flags        = CLKDM_CAN_SWSUP,
0410 };
0411 
0412 static struct clockdomain l3main1_7xx_clkdm = {
0413     .name         = "l3main1_clkdm",
0414     .pwrdm        = { .name = "core_pwrdm" },
0415     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0416     .cm_inst      = DRA7XX_CM_CORE_CORE_INST,
0417     .clkdm_offs   = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
0418     .dep_bit      = DRA7XX_L3MAIN1_STATDEP_SHIFT,
0419     .flags        = CLKDM_CAN_HWSUP,
0420 };
0421 
0422 static struct clockdomain vpe_7xx_clkdm = {
0423     .name         = "vpe_clkdm",
0424     .pwrdm        = { .name = "vpe_pwrdm" },
0425     .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
0426     .cm_inst      = DRA7XX_CM_CORE_AON_VPE_INST,
0427     .clkdm_offs   = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS,
0428     .dep_bit      = DRA7XX_VPE_STATDEP_SHIFT,
0429     .wkdep_srcs   = vpe_wkup_sleep_deps,
0430     .sleepdep_srcs    = vpe_wkup_sleep_deps,
0431     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0432 };
0433 
0434 static struct clockdomain mpu_7xx_clkdm = {
0435     .name         = "mpu_clkdm",
0436     .pwrdm        = { .name = "mpu_pwrdm" },
0437     .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
0438     .cm_inst      = DRA7XX_CM_CORE_AON_MPU_INST,
0439     .clkdm_offs   = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS,
0440     .wkdep_srcs   = mpu_wkup_sleep_deps,
0441     .sleepdep_srcs    = mpu_wkup_sleep_deps,
0442     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0443 };
0444 
0445 static struct clockdomain custefuse_7xx_clkdm = {
0446     .name         = "custefuse_clkdm",
0447     .pwrdm        = { .name = "custefuse_pwrdm" },
0448     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0449     .cm_inst      = DRA7XX_CM_CORE_CUSTEFUSE_INST,
0450     .clkdm_offs   = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
0451     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0452 };
0453 
0454 static struct clockdomain ipu_7xx_clkdm = {
0455     .name         = "ipu_clkdm",
0456     .pwrdm        = { .name = "ipu_pwrdm" },
0457     .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
0458     .cm_inst      = DRA7XX_CM_CORE_AON_IPU_INST,
0459     .clkdm_offs   = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
0460     .dep_bit      = DRA7XX_IPU_STATDEP_SHIFT,
0461     .flags        = CLKDM_CAN_SWSUP,
0462 };
0463 
0464 static struct clockdomain mpu1_7xx_clkdm = {
0465     .name         = "mpu1_clkdm",
0466     .pwrdm        = { .name = "cpu1_pwrdm" },
0467     .prcm_partition   = DRA7XX_MPU_PRCM_PARTITION,
0468     .cm_inst      = DRA7XX_MPU_PRCM_CM_C1_INST,
0469     .clkdm_offs   = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS,
0470     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0471 };
0472 
0473 static struct clockdomain gmac_7xx_clkdm = {
0474     .name         = "gmac_clkdm",
0475     .pwrdm        = { .name = "l3init_pwrdm" },
0476     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0477     .cm_inst      = DRA7XX_CM_CORE_L3INIT_INST,
0478     .clkdm_offs   = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS,
0479     .dep_bit      = DRA7XX_GMAC_STATDEP_SHIFT,
0480     .wkdep_srcs   = gmac_wkup_sleep_deps,
0481     .sleepdep_srcs    = gmac_wkup_sleep_deps,
0482     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0483 };
0484 
0485 static struct clockdomain l4cfg_7xx_clkdm = {
0486     .name         = "l4cfg_clkdm",
0487     .pwrdm        = { .name = "core_pwrdm" },
0488     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0489     .cm_inst      = DRA7XX_CM_CORE_CORE_INST,
0490     .clkdm_offs   = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS,
0491     .dep_bit      = DRA7XX_L4CFG_STATDEP_SHIFT,
0492     .flags        = CLKDM_CAN_HWSUP,
0493 };
0494 
0495 static struct clockdomain dma_7xx_clkdm = {
0496     .name         = "dma_clkdm",
0497     .pwrdm        = { .name = "core_pwrdm" },
0498     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0499     .cm_inst      = DRA7XX_CM_CORE_CORE_INST,
0500     .clkdm_offs   = DRA7XX_CM_CORE_CORE_DMA_CDOFFS,
0501     .wkdep_srcs   = dma_wkup_sleep_deps,
0502     .sleepdep_srcs    = dma_wkup_sleep_deps,
0503     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0504 };
0505 
0506 static struct clockdomain rtc_7xx_clkdm = {
0507     .name         = "rtc_clkdm",
0508     .pwrdm        = { .name = "rtc_pwrdm" },
0509     .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
0510     .cm_inst      = DRA7XX_CM_CORE_AON_RTC_INST,
0511     .clkdm_offs   = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS,
0512     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0513 };
0514 
0515 static struct clockdomain pcie_7xx_clkdm = {
0516     .name         = "pcie_clkdm",
0517     .pwrdm        = { .name = "l3init_pwrdm" },
0518     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0519     .cm_inst      = DRA7XX_CM_CORE_L3INIT_INST,
0520     .clkdm_offs   = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS,
0521     .dep_bit      = DRA7XX_PCIE_STATDEP_SHIFT,
0522     .wkdep_srcs   = pcie_wkup_sleep_deps,
0523     .sleepdep_srcs    = pcie_wkup_sleep_deps,
0524     .flags        = CLKDM_CAN_SWSUP,
0525 };
0526 
0527 static struct clockdomain atl_7xx_clkdm = {
0528     .name         = "atl_clkdm",
0529     .pwrdm        = { .name = "core_pwrdm" },
0530     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0531     .cm_inst      = DRA7XX_CM_CORE_CORE_INST,
0532     .clkdm_offs   = DRA7XX_CM_CORE_CORE_ATL_CDOFFS,
0533     .dep_bit      = DRA7XX_ATL_STATDEP_SHIFT,
0534     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0535 };
0536 
0537 static struct clockdomain l3instr_7xx_clkdm = {
0538     .name         = "l3instr_clkdm",
0539     .pwrdm        = { .name = "core_pwrdm" },
0540     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0541     .cm_inst      = DRA7XX_CM_CORE_CORE_INST,
0542     .clkdm_offs   = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS,
0543 };
0544 
0545 static struct clockdomain dss_7xx_clkdm = {
0546     .name         = "dss_clkdm",
0547     .pwrdm        = { .name = "dss_pwrdm" },
0548     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0549     .cm_inst      = DRA7XX_CM_CORE_DSS_INST,
0550     .clkdm_offs   = DRA7XX_CM_CORE_DSS_DSS_CDOFFS,
0551     .dep_bit      = DRA7XX_DSS_STATDEP_SHIFT,
0552     .wkdep_srcs   = dss_wkup_sleep_deps,
0553     .sleepdep_srcs    = dss_wkup_sleep_deps,
0554     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0555 };
0556 
0557 static struct clockdomain emif_7xx_clkdm = {
0558     .name         = "emif_clkdm",
0559     .pwrdm        = { .name = "core_pwrdm" },
0560     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0561     .cm_inst      = DRA7XX_CM_CORE_CORE_INST,
0562     .clkdm_offs   = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS,
0563     .dep_bit      = DRA7XX_EMIF_STATDEP_SHIFT,
0564     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0565 };
0566 
0567 static struct clockdomain emu_7xx_clkdm = {
0568     .name         = "emu_clkdm",
0569     .pwrdm        = { .name = "emu_pwrdm" },
0570     .prcm_partition   = DRA7XX_PRM_PARTITION,
0571     .cm_inst      = DRA7XX_PRM_EMU_CM_INST,
0572     .clkdm_offs   = DRA7XX_PRM_EMU_CM_EMU_CDOFFS,
0573     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0574 };
0575 
0576 static struct clockdomain dsp2_7xx_clkdm = {
0577     .name         = "dsp2_clkdm",
0578     .pwrdm        = { .name = "dsp2_pwrdm" },
0579     .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
0580     .cm_inst      = DRA7XX_CM_CORE_AON_DSP2_INST,
0581     .clkdm_offs   = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS,
0582     .dep_bit      = DRA7XX_DSP2_STATDEP_SHIFT,
0583     .wkdep_srcs   = dsp2_wkup_sleep_deps,
0584     .sleepdep_srcs    = dsp2_wkup_sleep_deps,
0585     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0586 };
0587 
0588 static struct clockdomain dsp1_7xx_clkdm = {
0589     .name         = "dsp1_clkdm",
0590     .pwrdm        = { .name = "dsp1_pwrdm" },
0591     .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
0592     .cm_inst      = DRA7XX_CM_CORE_AON_DSP1_INST,
0593     .clkdm_offs   = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS,
0594     .dep_bit      = DRA7XX_DSP1_STATDEP_SHIFT,
0595     .wkdep_srcs   = dsp1_wkup_sleep_deps,
0596     .sleepdep_srcs    = dsp1_wkup_sleep_deps,
0597     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0598 };
0599 
0600 static struct clockdomain cam_7xx_clkdm = {
0601     .name         = "cam_clkdm",
0602     .pwrdm        = { .name = "cam_pwrdm" },
0603     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0604     .cm_inst      = DRA7XX_CM_CORE_CAM_INST,
0605     .clkdm_offs   = DRA7XX_CM_CORE_CAM_CAM_CDOFFS,
0606     .dep_bit      = DRA7XX_CAM_STATDEP_SHIFT,
0607     .wkdep_srcs   = cam_wkup_sleep_deps,
0608     .sleepdep_srcs    = cam_wkup_sleep_deps,
0609     .flags        = CLKDM_CAN_SWSUP,
0610 };
0611 
0612 static struct clockdomain l4per_7xx_clkdm = {
0613     .name         = "l4per_clkdm",
0614     .pwrdm        = { .name = "l4per_pwrdm" },
0615     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0616     .cm_inst      = DRA7XX_CM_CORE_L4PER_INST,
0617     .clkdm_offs   = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS,
0618     .dep_bit      = DRA7XX_L4PER_STATDEP_SHIFT,
0619     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0620 };
0621 
0622 static struct clockdomain gpu_7xx_clkdm = {
0623     .name         = "gpu_clkdm",
0624     .pwrdm        = { .name = "gpu_pwrdm" },
0625     .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
0626     .cm_inst      = DRA7XX_CM_CORE_GPU_INST,
0627     .clkdm_offs   = DRA7XX_CM_CORE_GPU_GPU_CDOFFS,
0628     .dep_bit      = DRA7XX_GPU_STATDEP_SHIFT,
0629     .wkdep_srcs   = gpu_wkup_sleep_deps,
0630     .sleepdep_srcs    = gpu_wkup_sleep_deps,
0631     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0632 };
0633 
0634 static struct clockdomain eve4_7xx_clkdm = {
0635     .name         = "eve4_clkdm",
0636     .pwrdm        = { .name = "eve4_pwrdm" },
0637     .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
0638     .cm_inst      = DRA7XX_CM_CORE_AON_EVE4_INST,
0639     .clkdm_offs   = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS,
0640     .dep_bit      = DRA7XX_EVE4_STATDEP_SHIFT,
0641     .wkdep_srcs   = eve4_wkup_sleep_deps,
0642     .sleepdep_srcs    = eve4_wkup_sleep_deps,
0643     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0644 };
0645 
0646 static struct clockdomain eve2_7xx_clkdm = {
0647     .name         = "eve2_clkdm",
0648     .pwrdm        = { .name = "eve2_pwrdm" },
0649     .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
0650     .cm_inst      = DRA7XX_CM_CORE_AON_EVE2_INST,
0651     .clkdm_offs   = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS,
0652     .dep_bit      = DRA7XX_EVE2_STATDEP_SHIFT,
0653     .wkdep_srcs   = eve2_wkup_sleep_deps,
0654     .sleepdep_srcs    = eve2_wkup_sleep_deps,
0655     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0656 };
0657 
0658 static struct clockdomain eve3_7xx_clkdm = {
0659     .name         = "eve3_clkdm",
0660     .pwrdm        = { .name = "eve3_pwrdm" },
0661     .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
0662     .cm_inst      = DRA7XX_CM_CORE_AON_EVE3_INST,
0663     .clkdm_offs   = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS,
0664     .dep_bit      = DRA7XX_EVE3_STATDEP_SHIFT,
0665     .wkdep_srcs   = eve3_wkup_sleep_deps,
0666     .sleepdep_srcs    = eve3_wkup_sleep_deps,
0667     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0668 };
0669 
0670 static struct clockdomain wkupaon_7xx_clkdm = {
0671     .name         = "wkupaon_clkdm",
0672     .pwrdm        = { .name = "wkupaon_pwrdm" },
0673     .prcm_partition   = DRA7XX_PRM_PARTITION,
0674     .cm_inst      = DRA7XX_PRM_WKUPAON_CM_INST,
0675     .clkdm_offs   = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
0676     .dep_bit      = DRA7XX_WKUPAON_STATDEP_SHIFT,
0677     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0678 };
0679 
0680 static struct clockdomain eve1_7xx_clkdm = {
0681     .name         = "eve1_clkdm",
0682     .pwrdm        = { .name = "eve1_pwrdm" },
0683     .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
0684     .cm_inst      = DRA7XX_CM_CORE_AON_EVE1_INST,
0685     .clkdm_offs   = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS,
0686     .dep_bit      = DRA7XX_EVE1_STATDEP_SHIFT,
0687     .wkdep_srcs   = eve1_wkup_sleep_deps,
0688     .sleepdep_srcs    = eve1_wkup_sleep_deps,
0689     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0690 };
0691 
0692 /* As clockdomains are added or removed above, this list must also be changed */
0693 static struct clockdomain *clockdomains_dra7xx[] __initdata = {
0694     &l4per3_7xx_clkdm,
0695     &l4per2_7xx_clkdm,
0696     &mpu0_7xx_clkdm,
0697     &iva_7xx_clkdm,
0698     &coreaon_7xx_clkdm,
0699     &ipu1_7xx_clkdm,
0700     &ipu2_7xx_clkdm,
0701     &l3init_7xx_clkdm,
0702     &l4sec_7xx_clkdm,
0703     &l3main1_7xx_clkdm,
0704     &vpe_7xx_clkdm,
0705     &mpu_7xx_clkdm,
0706     &custefuse_7xx_clkdm,
0707     &ipu_7xx_clkdm,
0708     &mpu1_7xx_clkdm,
0709     &gmac_7xx_clkdm,
0710     &l4cfg_7xx_clkdm,
0711     &dma_7xx_clkdm,
0712     &rtc_7xx_clkdm,
0713     &pcie_7xx_clkdm,
0714     &atl_7xx_clkdm,
0715     &l3instr_7xx_clkdm,
0716     &dss_7xx_clkdm,
0717     &emif_7xx_clkdm,
0718     &emu_7xx_clkdm,
0719     &dsp2_7xx_clkdm,
0720     &dsp1_7xx_clkdm,
0721     &cam_7xx_clkdm,
0722     &l4per_7xx_clkdm,
0723     &gpu_7xx_clkdm,
0724     &eve4_7xx_clkdm,
0725     &eve2_7xx_clkdm,
0726     &eve3_7xx_clkdm,
0727     &wkupaon_7xx_clkdm,
0728     &eve1_7xx_clkdm,
0729     NULL
0730 };
0731 
0732 void __init dra7xx_clockdomains_init(void)
0733 {
0734     clkdm_register_platform_funcs(&omap4_clkdm_operations);
0735     clkdm_register_clkdms(clockdomains_dra7xx);
0736     clkdm_complete_init();
0737 }
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