arm/mach-omap2/clockdomains54xx_data.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * OMAP54XX Clock domains framework
0004  *
0005  * Copyright (C) 2013 Texas Instruments, Inc.
0006  *
0007  * Abhijit Pagare (abhijitpagare@ti.com)
0008  * Benoit Cousson (b-cousson@ti.com)
0009  * Paul Walmsley (paul@pwsan.com)
0010  *
0011  * This file is automatically generated from the OMAP hardware databases.
0012  * We respectfully ask that any modifications to this file be coordinated
0013  * with the public linux-omap@vger.kernel.org mailing list and the
0014  * authors above to ensure that the autogeneration scripts are kept
0015  * up-to-date with the file contents.
0016  */
0017
0018 #include <linux/kernel.h>
0019 #include <linux/io.h>
0020
0021 #include "clockdomain.h"
0022 #include "cm1_54xx.h"
0023 #include "cm2_54xx.h"
0024
0025 #include "cm-regbits-54xx.h"
0026 #include "prm54xx.h"
0027 #include "prcm44xx.h"
0028 #include "prcm_mpu54xx.h"
0029
0030 /* Static Dependencies for OMAP4 Clock Domains */
0031
0032 static struct clkdm_dep c2c_wkup_sleep_deps[] = {
0033     { .clkdm_name = "abe_clkdm" },
0034     { .clkdm_name = "emif_clkdm" },
0035     { .clkdm_name = "iva_clkdm" },
0036     { .clkdm_name = "l3init_clkdm" },
0037     { .clkdm_name = "l3main1_clkdm" },
0038     { .clkdm_name = "l3main2_clkdm" },
0039     { .clkdm_name = "l4cfg_clkdm" },
0040     { .clkdm_name = "l4per_clkdm" },
0041     { NULL },
0042 };
0043
0044 static struct clkdm_dep cam_wkup_sleep_deps[] = {
0045     { .clkdm_name = "emif_clkdm" },
0046     { .clkdm_name = "iva_clkdm" },
0047     { .clkdm_name = "l3main1_clkdm" },
0048     { NULL },
0049 };
0050
0051 static struct clkdm_dep dma_wkup_sleep_deps[] = {
0052     { .clkdm_name = "abe_clkdm" },
0053     { .clkdm_name = "dss_clkdm" },
0054     { .clkdm_name = "emif_clkdm" },
0055     { .clkdm_name = "ipu_clkdm" },
0056     { .clkdm_name = "iva_clkdm" },
0057     { .clkdm_name = "l3init_clkdm" },
0058     { .clkdm_name = "l3main1_clkdm" },
0059     { .clkdm_name = "l4cfg_clkdm" },
0060     { .clkdm_name = "l4per_clkdm" },
0061     { .clkdm_name = "l4sec_clkdm" },
0062     { .clkdm_name = "wkupaon_clkdm" },
0063     { NULL },
0064 };
0065
0066 static struct clkdm_dep dsp_wkup_sleep_deps[] = {
0067     { .clkdm_name = "abe_clkdm" },
0068     { .clkdm_name = "emif_clkdm" },
0069     { .clkdm_name = "iva_clkdm" },
0070     { .clkdm_name = "l3init_clkdm" },
0071     { .clkdm_name = "l3main1_clkdm" },
0072     { .clkdm_name = "l3main2_clkdm" },
0073     { .clkdm_name = "l4cfg_clkdm" },
0074     { .clkdm_name = "l4per_clkdm" },
0075     { .clkdm_name = "wkupaon_clkdm" },
0076     { NULL },
0077 };
0078
0079 static struct clkdm_dep dss_wkup_sleep_deps[] = {
0080     { .clkdm_name = "emif_clkdm" },
0081     { .clkdm_name = "iva_clkdm" },
0082     { .clkdm_name = "l3main2_clkdm" },
0083     { NULL },
0084 };
0085
0086 static struct clkdm_dep gpu_wkup_sleep_deps[] = {
0087     { .clkdm_name = "emif_clkdm" },
0088     { .clkdm_name = "iva_clkdm" },
0089     { .clkdm_name = "l3main1_clkdm" },
0090     { NULL },
0091 };
0092
0093 static struct clkdm_dep ipu_wkup_sleep_deps[] = {
0094     { .clkdm_name = "abe_clkdm" },
0095     { .clkdm_name = "dsp_clkdm" },
0096     { .clkdm_name = "dss_clkdm" },
0097     { .clkdm_name = "emif_clkdm" },
0098     { .clkdm_name = "gpu_clkdm" },
0099     { .clkdm_name = "iva_clkdm" },
0100     { .clkdm_name = "l3init_clkdm" },
0101     { .clkdm_name = "l3main1_clkdm" },
0102     { .clkdm_name = "l3main2_clkdm" },
0103     { .clkdm_name = "l4cfg_clkdm" },
0104     { .clkdm_name = "l4per_clkdm" },
0105     { .clkdm_name = "l4sec_clkdm" },
0106     { .clkdm_name = "wkupaon_clkdm" },
0107     { NULL },
0108 };
0109
0110 static struct clkdm_dep iva_wkup_sleep_deps[] = {
0111     { .clkdm_name = "emif_clkdm" },
0112     { .clkdm_name = "l3main1_clkdm" },
0113     { NULL },
0114 };
0115
0116 static struct clkdm_dep l3init_wkup_sleep_deps[] = {
0117     { .clkdm_name = "abe_clkdm" },
0118     { .clkdm_name = "emif_clkdm" },
0119     { .clkdm_name = "iva_clkdm" },
0120     { .clkdm_name = "l4cfg_clkdm" },
0121     { .clkdm_name = "l4per_clkdm" },
0122     { .clkdm_name = "l4sec_clkdm" },
0123     { .clkdm_name = "wkupaon_clkdm" },
0124     { NULL },
0125 };
0126
0127 static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
0128     { .clkdm_name = "emif_clkdm" },
0129     { .clkdm_name = "l3main1_clkdm" },
0130     { .clkdm_name = "l4per_clkdm" },
0131     { NULL },
0132 };
0133
0134 static struct clkdm_dep mipiext_wkup_sleep_deps[] = {
0135     { .clkdm_name = "abe_clkdm" },
0136     { .clkdm_name = "emif_clkdm" },
0137     { .clkdm_name = "iva_clkdm" },
0138     { .clkdm_name = "l3init_clkdm" },
0139     { .clkdm_name = "l3main1_clkdm" },
0140     { .clkdm_name = "l3main2_clkdm" },
0141     { .clkdm_name = "l4cfg_clkdm" },
0142     { .clkdm_name = "l4per_clkdm" },
0143     { NULL },
0144 };
0145
0146 static struct clkdm_dep mpu_wkup_sleep_deps[] = {
0147     { .clkdm_name = "abe_clkdm" },
0148     { .clkdm_name = "dsp_clkdm" },
0149     { .clkdm_name = "dss_clkdm" },
0150     { .clkdm_name = "emif_clkdm" },
0151     { .clkdm_name = "gpu_clkdm" },
0152     { .clkdm_name = "ipu_clkdm" },
0153     { .clkdm_name = "iva_clkdm" },
0154     { .clkdm_name = "l3init_clkdm" },
0155     { .clkdm_name = "l3main1_clkdm" },
0156     { .clkdm_name = "l3main2_clkdm" },
0157     { .clkdm_name = "l4cfg_clkdm" },
0158     { .clkdm_name = "l4per_clkdm" },
0159     { .clkdm_name = "l4sec_clkdm" },
0160     { .clkdm_name = "wkupaon_clkdm" },
0161     { NULL },
0162 };
0163
0164 static struct clockdomain l4sec_54xx_clkdm = {
0165     .name         = "l4sec_clkdm",
0166     .pwrdm        = { .name = "core_pwrdm" },
0167     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0168     .cm_inst      = OMAP54XX_CM_CORE_CORE_INST,
0169     .clkdm_offs   = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS,
0170     .dep_bit      = OMAP54XX_L4SEC_STATDEP_SHIFT,
0171     .wkdep_srcs   = l4sec_wkup_sleep_deps,
0172     .sleepdep_srcs    = l4sec_wkup_sleep_deps,
0173     .flags        = CLKDM_CAN_SWSUP,
0174 };
0175
0176 static struct clockdomain iva_54xx_clkdm = {
0177     .name         = "iva_clkdm",
0178     .pwrdm        = { .name = "iva_pwrdm" },
0179     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0180     .cm_inst      = OMAP54XX_CM_CORE_IVA_INST,
0181     .clkdm_offs   = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS,
0182     .dep_bit      = OMAP54XX_IVA_STATDEP_SHIFT,
0183     .wkdep_srcs   = iva_wkup_sleep_deps,
0184     .sleepdep_srcs    = iva_wkup_sleep_deps,
0185     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0186 };
0187
0188 static struct clockdomain mipiext_54xx_clkdm = {
0189     .name         = "mipiext_clkdm",
0190     .pwrdm        = { .name = "core_pwrdm" },
0191     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0192     .cm_inst      = OMAP54XX_CM_CORE_CORE_INST,
0193     .clkdm_offs   = OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS,
0194     .wkdep_srcs   = mipiext_wkup_sleep_deps,
0195     .sleepdep_srcs    = mipiext_wkup_sleep_deps,
0196     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0197 };
0198
0199 static struct clockdomain l3main2_54xx_clkdm = {
0200     .name         = "l3main2_clkdm",
0201     .pwrdm        = { .name = "core_pwrdm" },
0202     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0203     .cm_inst      = OMAP54XX_CM_CORE_CORE_INST,
0204     .clkdm_offs   = OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS,
0205     .dep_bit      = OMAP54XX_L3MAIN2_STATDEP_SHIFT,
0206     .flags        = CLKDM_CAN_HWSUP,
0207 };
0208
0209 static struct clockdomain l3main1_54xx_clkdm = {
0210     .name         = "l3main1_clkdm",
0211     .pwrdm        = { .name = "core_pwrdm" },
0212     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0213     .cm_inst      = OMAP54XX_CM_CORE_CORE_INST,
0214     .clkdm_offs   = OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
0215     .dep_bit      = OMAP54XX_L3MAIN1_STATDEP_SHIFT,
0216     .flags        = CLKDM_CAN_HWSUP,
0217 };
0218
0219 static struct clockdomain custefuse_54xx_clkdm = {
0220     .name         = "custefuse_clkdm",
0221     .pwrdm        = { .name = "custefuse_pwrdm" },
0222     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0223     .cm_inst      = OMAP54XX_CM_CORE_CUSTEFUSE_INST,
0224     .clkdm_offs   = OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
0225     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0226 };
0227
0228 static struct clockdomain ipu_54xx_clkdm = {
0229     .name         = "ipu_clkdm",
0230     .pwrdm        = { .name = "core_pwrdm" },
0231     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0232     .cm_inst      = OMAP54XX_CM_CORE_CORE_INST,
0233     .clkdm_offs   = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS,
0234     .dep_bit      = OMAP54XX_IPU_STATDEP_SHIFT,
0235     .wkdep_srcs   = ipu_wkup_sleep_deps,
0236     .sleepdep_srcs    = ipu_wkup_sleep_deps,
0237     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0238 };
0239
0240 static struct clockdomain l4cfg_54xx_clkdm = {
0241     .name         = "l4cfg_clkdm",
0242     .pwrdm        = { .name = "core_pwrdm" },
0243     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0244     .cm_inst      = OMAP54XX_CM_CORE_CORE_INST,
0245     .clkdm_offs   = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS,
0246     .dep_bit      = OMAP54XX_L4CFG_STATDEP_SHIFT,
0247     .flags        = CLKDM_CAN_HWSUP,
0248 };
0249
0250 static struct clockdomain abe_54xx_clkdm = {
0251     .name         = "abe_clkdm",
0252     .pwrdm        = { .name = "abe_pwrdm" },
0253     .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
0254     .cm_inst      = OMAP54XX_CM_CORE_AON_ABE_INST,
0255     .clkdm_offs   = OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS,
0256     .dep_bit      = OMAP54XX_ABE_STATDEP_SHIFT,
0257     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0258 };
0259
0260 static struct clockdomain dss_54xx_clkdm = {
0261     .name         = "dss_clkdm",
0262     .pwrdm        = { .name = "dss_pwrdm" },
0263     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0264     .cm_inst      = OMAP54XX_CM_CORE_DSS_INST,
0265     .clkdm_offs   = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS,
0266     .dep_bit      = OMAP54XX_DSS_STATDEP_SHIFT,
0267     .wkdep_srcs   = dss_wkup_sleep_deps,
0268     .sleepdep_srcs    = dss_wkup_sleep_deps,
0269     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0270 };
0271
0272 static struct clockdomain dsp_54xx_clkdm = {
0273     .name         = "dsp_clkdm",
0274     .pwrdm        = { .name = "dsp_pwrdm" },
0275     .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
0276     .cm_inst      = OMAP54XX_CM_CORE_AON_DSP_INST,
0277     .clkdm_offs   = OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS,
0278     .dep_bit      = OMAP54XX_DSP_STATDEP_SHIFT,
0279     .wkdep_srcs   = dsp_wkup_sleep_deps,
0280     .sleepdep_srcs    = dsp_wkup_sleep_deps,
0281     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0282 };
0283
0284 static struct clockdomain c2c_54xx_clkdm = {
0285     .name         = "c2c_clkdm",
0286     .pwrdm        = { .name = "core_pwrdm" },
0287     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0288     .cm_inst      = OMAP54XX_CM_CORE_CORE_INST,
0289     .clkdm_offs   = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS,
0290     .wkdep_srcs   = c2c_wkup_sleep_deps,
0291     .sleepdep_srcs    = c2c_wkup_sleep_deps,
0292     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0293 };
0294
0295 static struct clockdomain l4per_54xx_clkdm = {
0296     .name         = "l4per_clkdm",
0297     .pwrdm        = { .name = "core_pwrdm" },
0298     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0299     .cm_inst      = OMAP54XX_CM_CORE_CORE_INST,
0300     .clkdm_offs   = OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS,
0301     .dep_bit      = OMAP54XX_L4PER_STATDEP_SHIFT,
0302     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0303 };
0304
0305 static struct clockdomain gpu_54xx_clkdm = {
0306     .name         = "gpu_clkdm",
0307     .pwrdm        = { .name = "gpu_pwrdm" },
0308     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0309     .cm_inst      = OMAP54XX_CM_CORE_GPU_INST,
0310     .clkdm_offs   = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS,
0311     .dep_bit      = OMAP54XX_GPU_STATDEP_SHIFT,
0312     .wkdep_srcs   = gpu_wkup_sleep_deps,
0313     .sleepdep_srcs    = gpu_wkup_sleep_deps,
0314     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0315 };
0316
0317 static struct clockdomain wkupaon_54xx_clkdm = {
0318     .name         = "wkupaon_clkdm",
0319     .pwrdm        = { .name = "wkupaon_pwrdm" },
0320     .prcm_partition   = OMAP54XX_PRM_PARTITION,
0321     .cm_inst      = OMAP54XX_PRM_WKUPAON_CM_INST,
0322     .clkdm_offs   = OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
0323     .dep_bit      = OMAP54XX_WKUPAON_STATDEP_SHIFT,
0324     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0325 };
0326
0327 static struct clockdomain mpu0_54xx_clkdm = {
0328     .name         = "mpu0_clkdm",
0329     .pwrdm        = { .name = "cpu0_pwrdm" },
0330     .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
0331     .cm_inst      = OMAP54XX_PRCM_MPU_CM_C0_INST,
0332     .clkdm_offs   = OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS,
0333     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0334 };
0335
0336 static struct clockdomain mpu1_54xx_clkdm = {
0337     .name         = "mpu1_clkdm",
0338     .pwrdm        = { .name = "cpu1_pwrdm" },
0339     .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
0340     .cm_inst      = OMAP54XX_PRCM_MPU_CM_C1_INST,
0341     .clkdm_offs   = OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS,
0342     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0343 };
0344
0345 static struct clockdomain coreaon_54xx_clkdm = {
0346     .name         = "coreaon_clkdm",
0347     .pwrdm        = { .name = "coreaon_pwrdm" },
0348     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0349     .cm_inst      = OMAP54XX_CM_CORE_COREAON_INST,
0350     .clkdm_offs   = OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS,
0351     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0352 };
0353
0354 static struct clockdomain mpu_54xx_clkdm = {
0355     .name         = "mpu_clkdm",
0356     .pwrdm        = { .name = "mpu_pwrdm" },
0357     .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
0358     .cm_inst      = OMAP54XX_CM_CORE_AON_MPU_INST,
0359     .clkdm_offs   = OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS,
0360     .wkdep_srcs   = mpu_wkup_sleep_deps,
0361     .sleepdep_srcs    = mpu_wkup_sleep_deps,
0362     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0363 };
0364
0365 static struct clockdomain l3init_54xx_clkdm = {
0366     .name         = "l3init_clkdm",
0367     .pwrdm        = { .name = "l3init_pwrdm" },
0368     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0369     .cm_inst      = OMAP54XX_CM_CORE_L3INIT_INST,
0370     .clkdm_offs   = OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
0371     .dep_bit      = OMAP54XX_L3INIT_STATDEP_SHIFT,
0372     .wkdep_srcs   = l3init_wkup_sleep_deps,
0373     .sleepdep_srcs    = l3init_wkup_sleep_deps,
0374     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0375 };
0376
0377 static struct clockdomain dma_54xx_clkdm = {
0378     .name         = "dma_clkdm",
0379     .pwrdm        = { .name = "core_pwrdm" },
0380     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0381     .cm_inst      = OMAP54XX_CM_CORE_CORE_INST,
0382     .clkdm_offs   = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS,
0383     .wkdep_srcs   = dma_wkup_sleep_deps,
0384     .sleepdep_srcs    = dma_wkup_sleep_deps,
0385     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0386 };
0387
0388 static struct clockdomain l3instr_54xx_clkdm = {
0389     .name         = "l3instr_clkdm",
0390     .pwrdm        = { .name = "core_pwrdm" },
0391     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0392     .cm_inst      = OMAP54XX_CM_CORE_CORE_INST,
0393     .clkdm_offs   = OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS,
0394 };
0395
0396 static struct clockdomain emif_54xx_clkdm = {
0397     .name         = "emif_clkdm",
0398     .pwrdm        = { .name = "core_pwrdm" },
0399     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0400     .cm_inst      = OMAP54XX_CM_CORE_CORE_INST,
0401     .clkdm_offs   = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS,
0402     .dep_bit      = OMAP54XX_EMIF_STATDEP_SHIFT,
0403     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0404 };
0405
0406 static struct clockdomain emu_54xx_clkdm = {
0407     .name         = "emu_clkdm",
0408     .pwrdm        = { .name = "emu_pwrdm" },
0409     .prcm_partition   = OMAP54XX_PRM_PARTITION,
0410     .cm_inst      = OMAP54XX_PRM_EMU_CM_INST,
0411     .clkdm_offs   = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS,
0412     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0413 };
0414
0415 static struct clockdomain cam_54xx_clkdm = {
0416     .name         = "cam_clkdm",
0417     .pwrdm        = { .name = "cam_pwrdm" },
0418     .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
0419     .cm_inst      = OMAP54XX_CM_CORE_CAM_INST,
0420     .clkdm_offs   = OMAP54XX_CM_CORE_CAM_CAM_CDOFFS,
0421     .wkdep_srcs   = cam_wkup_sleep_deps,
0422     .sleepdep_srcs    = cam_wkup_sleep_deps,
0423     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0424 };
0425
0426 /* As clockdomains are added or removed above, this list must also be changed */
0427 static struct clockdomain *clockdomains_omap54xx[] __initdata = {
0428     &l4sec_54xx_clkdm,
0429     &iva_54xx_clkdm,
0430     &mipiext_54xx_clkdm,
0431     &l3main2_54xx_clkdm,
0432     &l3main1_54xx_clkdm,
0433     &custefuse_54xx_clkdm,
0434     &ipu_54xx_clkdm,
0435     &l4cfg_54xx_clkdm,
0436     &abe_54xx_clkdm,
0437     &dss_54xx_clkdm,
0438     &dsp_54xx_clkdm,
0439     &c2c_54xx_clkdm,
0440     &l4per_54xx_clkdm,
0441     &gpu_54xx_clkdm,
0442     &wkupaon_54xx_clkdm,
0443     &mpu0_54xx_clkdm,
0444     &mpu1_54xx_clkdm,
0445     &coreaon_54xx_clkdm,
0446     &mpu_54xx_clkdm,
0447     &l3init_54xx_clkdm,
0448     &dma_54xx_clkdm,
0449     &l3instr_54xx_clkdm,
0450     &emif_54xx_clkdm,
0451     &emu_54xx_clkdm,
0452     &cam_54xx_clkdm,
0453     NULL
0454 };
0455
0456 void __init omap54xx_clockdomains_init(void)
0457 {
0458     clkdm_register_platform_funcs(&omap4_clkdm_operations);
0459     clkdm_register_clkdms(clockdomains_omap54xx);
0460     clkdm_complete_init();
0461 }