arm/mach-omap2/clockdomains44xx_data.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * OMAP4 Clock domains framework
0004  *
0005  * Copyright (C) 2009-2011 Texas Instruments, Inc.
0006  * Copyright (C) 2009-2011 Nokia Corporation
0007  *
0008  * Abhijit Pagare (abhijitpagare@ti.com)
0009  * Benoit Cousson (b-cousson@ti.com)
0010  * Paul Walmsley (paul@pwsan.com)
0011  *
0012  * This file is automatically generated from the OMAP hardware databases.
0013  * We respectfully ask that any modifications to this file be coordinated
0014  * with the public linux-omap@vger.kernel.org mailing list and the
0015  * authors above to ensure that the autogeneration scripts are kept
0016  * up-to-date with the file contents.
0017  */
0018
0019 #include <linux/kernel.h>
0020 #include <linux/io.h>
0021
0022 #include "clockdomain.h"
0023 #include "cm1_44xx.h"
0024 #include "cm2_44xx.h"
0025
0026 #include "cm-regbits-44xx.h"
0027 #include "prm44xx.h"
0028 #include "prcm44xx.h"
0029 #include "prcm_mpu44xx.h"
0030
0031 /* Static Dependencies for OMAP4 Clock Domains */
0032
0033 static struct clkdm_dep d2d_wkup_sleep_deps[] = {
0034     { .clkdm_name = "abe_clkdm" },
0035     { .clkdm_name = "ivahd_clkdm" },
0036     { .clkdm_name = "l3_1_clkdm" },
0037     { .clkdm_name = "l3_2_clkdm" },
0038     { .clkdm_name = "l3_emif_clkdm" },
0039     { .clkdm_name = "l3_init_clkdm" },
0040     { .clkdm_name = "l4_cfg_clkdm" },
0041     { .clkdm_name = "l4_per_clkdm" },
0042     { NULL },
0043 };
0044
0045 static struct clkdm_dep ducati_wkup_sleep_deps[] = {
0046     { .clkdm_name = "abe_clkdm" },
0047     { .clkdm_name = "ivahd_clkdm" },
0048     { .clkdm_name = "l3_1_clkdm" },
0049     { .clkdm_name = "l3_2_clkdm" },
0050     { .clkdm_name = "l3_dss_clkdm" },
0051     { .clkdm_name = "l3_emif_clkdm" },
0052     { .clkdm_name = "l3_gfx_clkdm" },
0053     { .clkdm_name = "l3_init_clkdm" },
0054     { .clkdm_name = "l4_cfg_clkdm" },
0055     { .clkdm_name = "l4_per_clkdm" },
0056     { .clkdm_name = "l4_secure_clkdm" },
0057     { .clkdm_name = "l4_wkup_clkdm" },
0058     { .clkdm_name = "tesla_clkdm" },
0059     { NULL },
0060 };
0061
0062 static struct clkdm_dep iss_wkup_sleep_deps[] = {
0063     { .clkdm_name = "ivahd_clkdm" },
0064     { .clkdm_name = "l3_1_clkdm" },
0065     { .clkdm_name = "l3_emif_clkdm" },
0066     { NULL },
0067 };
0068
0069 static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
0070     { .clkdm_name = "l3_1_clkdm" },
0071     { .clkdm_name = "l3_emif_clkdm" },
0072     { NULL },
0073 };
0074
0075 static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
0076     { .clkdm_name = "abe_clkdm" },
0077     { .clkdm_name = "ducati_clkdm" },
0078     { .clkdm_name = "ivahd_clkdm" },
0079     { .clkdm_name = "l3_1_clkdm" },
0080     { .clkdm_name = "l3_dss_clkdm" },
0081     { .clkdm_name = "l3_emif_clkdm" },
0082     { .clkdm_name = "l3_init_clkdm" },
0083     { .clkdm_name = "l4_cfg_clkdm" },
0084     { .clkdm_name = "l4_per_clkdm" },
0085     { .clkdm_name = "l4_secure_clkdm" },
0086     { .clkdm_name = "l4_wkup_clkdm" },
0087     { NULL },
0088 };
0089
0090 static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
0091     { .clkdm_name = "ivahd_clkdm" },
0092     { .clkdm_name = "l3_2_clkdm" },
0093     { .clkdm_name = "l3_emif_clkdm" },
0094     { NULL },
0095 };
0096
0097 static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
0098     { .clkdm_name = "ivahd_clkdm" },
0099     { .clkdm_name = "l3_1_clkdm" },
0100     { .clkdm_name = "l3_emif_clkdm" },
0101     { NULL },
0102 };
0103
0104 static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
0105     { .clkdm_name = "abe_clkdm" },
0106     { .clkdm_name = "ivahd_clkdm" },
0107     { .clkdm_name = "l3_emif_clkdm" },
0108     { .clkdm_name = "l4_cfg_clkdm" },
0109     { .clkdm_name = "l4_per_clkdm" },
0110     { .clkdm_name = "l4_secure_clkdm" },
0111     { .clkdm_name = "l4_wkup_clkdm" },
0112     { NULL },
0113 };
0114
0115 static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
0116     { .clkdm_name = "l3_1_clkdm" },
0117     { .clkdm_name = "l3_emif_clkdm" },
0118     { .clkdm_name = "l4_per_clkdm" },
0119     { NULL },
0120 };
0121
0122 static struct clkdm_dep mpu_wkup_sleep_deps[] = {
0123     { .clkdm_name = "abe_clkdm" },
0124     { .clkdm_name = "ducati_clkdm" },
0125     { .clkdm_name = "ivahd_clkdm" },
0126     { .clkdm_name = "l3_1_clkdm" },
0127     { .clkdm_name = "l3_2_clkdm" },
0128     { .clkdm_name = "l3_dss_clkdm" },
0129     { .clkdm_name = "l3_emif_clkdm" },
0130     { .clkdm_name = "l3_gfx_clkdm" },
0131     { .clkdm_name = "l3_init_clkdm" },
0132     { .clkdm_name = "l4_cfg_clkdm" },
0133     { .clkdm_name = "l4_per_clkdm" },
0134     { .clkdm_name = "l4_secure_clkdm" },
0135     { .clkdm_name = "l4_wkup_clkdm" },
0136     { .clkdm_name = "tesla_clkdm" },
0137     { NULL },
0138 };
0139
0140 static struct clkdm_dep tesla_wkup_sleep_deps[] = {
0141     { .clkdm_name = "abe_clkdm" },
0142     { .clkdm_name = "ivahd_clkdm" },
0143     { .clkdm_name = "l3_1_clkdm" },
0144     { .clkdm_name = "l3_2_clkdm" },
0145     { .clkdm_name = "l3_emif_clkdm" },
0146     { .clkdm_name = "l3_init_clkdm" },
0147     { .clkdm_name = "l4_cfg_clkdm" },
0148     { .clkdm_name = "l4_per_clkdm" },
0149     { .clkdm_name = "l4_wkup_clkdm" },
0150     { NULL },
0151 };
0152
0153 static struct clockdomain l4_cefuse_44xx_clkdm = {
0154     .name         = "l4_cefuse_clkdm",
0155     .pwrdm        = { .name = "cefuse_pwrdm" },
0156     .prcm_partition   = OMAP4430_CM2_PARTITION,
0157     .cm_inst      = OMAP4430_CM2_CEFUSE_INST,
0158     .clkdm_offs   = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
0159     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0160 };
0161
0162 static struct clockdomain l4_cfg_44xx_clkdm = {
0163     .name         = "l4_cfg_clkdm",
0164     .pwrdm        = { .name = "core_pwrdm" },
0165     .prcm_partition   = OMAP4430_CM2_PARTITION,
0166     .cm_inst      = OMAP4430_CM2_CORE_INST,
0167     .clkdm_offs   = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
0168     .dep_bit      = OMAP4430_L4CFG_STATDEP_SHIFT,
0169     .flags        = CLKDM_CAN_HWSUP,
0170 };
0171
0172 static struct clockdomain tesla_44xx_clkdm = {
0173     .name         = "tesla_clkdm",
0174     .pwrdm        = { .name = "tesla_pwrdm" },
0175     .prcm_partition   = OMAP4430_CM1_PARTITION,
0176     .cm_inst      = OMAP4430_CM1_TESLA_INST,
0177     .clkdm_offs   = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
0178     .dep_bit      = OMAP4430_TESLA_STATDEP_SHIFT,
0179     .wkdep_srcs   = tesla_wkup_sleep_deps,
0180     .sleepdep_srcs    = tesla_wkup_sleep_deps,
0181     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0182 };
0183
0184 static struct clockdomain l3_gfx_44xx_clkdm = {
0185     .name         = "l3_gfx_clkdm",
0186     .pwrdm        = { .name = "gfx_pwrdm" },
0187     .prcm_partition   = OMAP4430_CM2_PARTITION,
0188     .cm_inst      = OMAP4430_CM2_GFX_INST,
0189     .clkdm_offs   = OMAP4430_CM2_GFX_GFX_CDOFFS,
0190     .dep_bit      = OMAP4430_GFX_STATDEP_SHIFT,
0191     .wkdep_srcs   = l3_gfx_wkup_sleep_deps,
0192     .sleepdep_srcs    = l3_gfx_wkup_sleep_deps,
0193     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0194 };
0195
0196 static struct clockdomain ivahd_44xx_clkdm = {
0197     .name         = "ivahd_clkdm",
0198     .pwrdm        = { .name = "ivahd_pwrdm" },
0199     .prcm_partition   = OMAP4430_CM2_PARTITION,
0200     .cm_inst      = OMAP4430_CM2_IVAHD_INST,
0201     .clkdm_offs   = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
0202     .dep_bit      = OMAP4430_IVAHD_STATDEP_SHIFT,
0203     .wkdep_srcs   = ivahd_wkup_sleep_deps,
0204     .sleepdep_srcs    = ivahd_wkup_sleep_deps,
0205     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0206 };
0207
0208 static struct clockdomain l4_secure_44xx_clkdm = {
0209     .name         = "l4_secure_clkdm",
0210     .pwrdm        = { .name = "l4per_pwrdm" },
0211     .prcm_partition   = OMAP4430_CM2_PARTITION,
0212     .cm_inst      = OMAP4430_CM2_L4PER_INST,
0213     .clkdm_offs   = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
0214     .dep_bit      = OMAP4430_L4SEC_STATDEP_SHIFT,
0215     .wkdep_srcs   = l4_secure_wkup_sleep_deps,
0216     .sleepdep_srcs    = l4_secure_wkup_sleep_deps,
0217     .flags        = CLKDM_CAN_SWSUP,
0218 };
0219
0220 static struct clockdomain l4_per_44xx_clkdm = {
0221     .name         = "l4_per_clkdm",
0222     .pwrdm        = { .name = "l4per_pwrdm" },
0223     .prcm_partition   = OMAP4430_CM2_PARTITION,
0224     .cm_inst      = OMAP4430_CM2_L4PER_INST,
0225     .clkdm_offs   = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
0226     .dep_bit      = OMAP4430_L4PER_STATDEP_SHIFT,
0227     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0228 };
0229
0230 static struct clockdomain abe_44xx_clkdm = {
0231     .name         = "abe_clkdm",
0232     .pwrdm        = { .name = "abe_pwrdm" },
0233     .prcm_partition   = OMAP4430_CM1_PARTITION,
0234     .cm_inst      = OMAP4430_CM1_ABE_INST,
0235     .clkdm_offs   = OMAP4430_CM1_ABE_ABE_CDOFFS,
0236     .dep_bit      = OMAP4430_ABE_STATDEP_SHIFT,
0237     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0238 };
0239
0240 static struct clockdomain l3_instr_44xx_clkdm = {
0241     .name         = "l3_instr_clkdm",
0242     .pwrdm        = { .name = "core_pwrdm" },
0243     .prcm_partition   = OMAP4430_CM2_PARTITION,
0244     .cm_inst      = OMAP4430_CM2_CORE_INST,
0245     .clkdm_offs   = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
0246 };
0247
0248 static struct clockdomain l3_init_44xx_clkdm = {
0249     .name         = "l3_init_clkdm",
0250     .pwrdm        = { .name = "l3init_pwrdm" },
0251     .prcm_partition   = OMAP4430_CM2_PARTITION,
0252     .cm_inst      = OMAP4430_CM2_L3INIT_INST,
0253     .clkdm_offs   = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
0254     .dep_bit      = OMAP4430_L3INIT_STATDEP_SHIFT,
0255     .wkdep_srcs   = l3_init_wkup_sleep_deps,
0256     .sleepdep_srcs    = l3_init_wkup_sleep_deps,
0257     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0258 };
0259
0260 static struct clockdomain d2d_44xx_clkdm = {
0261     .name         = "d2d_clkdm",
0262     .pwrdm        = { .name = "core_pwrdm" },
0263     .prcm_partition   = OMAP4430_CM2_PARTITION,
0264     .cm_inst      = OMAP4430_CM2_CORE_INST,
0265     .clkdm_offs   = OMAP4430_CM2_CORE_D2D_CDOFFS,
0266     .wkdep_srcs   = d2d_wkup_sleep_deps,
0267     .sleepdep_srcs    = d2d_wkup_sleep_deps,
0268     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0269 };
0270
0271 static struct clockdomain mpu0_44xx_clkdm = {
0272     .name         = "mpu0_clkdm",
0273     .pwrdm        = { .name = "cpu0_pwrdm" },
0274     .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
0275     .cm_inst      = OMAP4430_PRCM_MPU_CPU0_INST,
0276     .clkdm_offs   = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
0277     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0278 };
0279
0280 static struct clockdomain mpu1_44xx_clkdm = {
0281     .name         = "mpu1_clkdm",
0282     .pwrdm        = { .name = "cpu1_pwrdm" },
0283     .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
0284     .cm_inst      = OMAP4430_PRCM_MPU_CPU1_INST,
0285     .clkdm_offs   = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
0286     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0287 };
0288
0289 static struct clockdomain l3_emif_44xx_clkdm = {
0290     .name         = "l3_emif_clkdm",
0291     .pwrdm        = { .name = "core_pwrdm" },
0292     .prcm_partition   = OMAP4430_CM2_PARTITION,
0293     .cm_inst      = OMAP4430_CM2_CORE_INST,
0294     .clkdm_offs   = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
0295     .dep_bit      = OMAP4430_MEMIF_STATDEP_SHIFT,
0296     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0297 };
0298
0299 static struct clockdomain l4_ao_44xx_clkdm = {
0300     .name         = "l4_ao_clkdm",
0301     .pwrdm        = { .name = "always_on_core_pwrdm" },
0302     .prcm_partition   = OMAP4430_CM2_PARTITION,
0303     .cm_inst      = OMAP4430_CM2_ALWAYS_ON_INST,
0304     .clkdm_offs   = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
0305     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0306 };
0307
0308 static struct clockdomain ducati_44xx_clkdm = {
0309     .name         = "ducati_clkdm",
0310     .pwrdm        = { .name = "core_pwrdm" },
0311     .prcm_partition   = OMAP4430_CM2_PARTITION,
0312     .cm_inst      = OMAP4430_CM2_CORE_INST,
0313     .clkdm_offs   = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
0314     .dep_bit      = OMAP4430_DUCATI_STATDEP_SHIFT,
0315     .wkdep_srcs   = ducati_wkup_sleep_deps,
0316     .sleepdep_srcs    = ducati_wkup_sleep_deps,
0317     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0318 };
0319
0320 static struct clockdomain mpu_44xx_clkdm = {
0321     .name         = "mpuss_clkdm",
0322     .pwrdm        = { .name = "mpu_pwrdm" },
0323     .prcm_partition   = OMAP4430_CM1_PARTITION,
0324     .cm_inst      = OMAP4430_CM1_MPU_INST,
0325     .clkdm_offs   = OMAP4430_CM1_MPU_MPU_CDOFFS,
0326     .wkdep_srcs   = mpu_wkup_sleep_deps,
0327     .sleepdep_srcs    = mpu_wkup_sleep_deps,
0328     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0329 };
0330
0331 static struct clockdomain l3_2_44xx_clkdm = {
0332     .name         = "l3_2_clkdm",
0333     .pwrdm        = { .name = "core_pwrdm" },
0334     .prcm_partition   = OMAP4430_CM2_PARTITION,
0335     .cm_inst      = OMAP4430_CM2_CORE_INST,
0336     .clkdm_offs   = OMAP4430_CM2_CORE_L3_2_CDOFFS,
0337     .dep_bit      = OMAP4430_L3_2_STATDEP_SHIFT,
0338     .flags        = CLKDM_CAN_HWSUP,
0339 };
0340
0341 static struct clockdomain l3_1_44xx_clkdm = {
0342     .name         = "l3_1_clkdm",
0343     .pwrdm        = { .name = "core_pwrdm" },
0344     .prcm_partition   = OMAP4430_CM2_PARTITION,
0345     .cm_inst      = OMAP4430_CM2_CORE_INST,
0346     .clkdm_offs   = OMAP4430_CM2_CORE_L3_1_CDOFFS,
0347     .dep_bit      = OMAP4430_L3_1_STATDEP_SHIFT,
0348     .flags        = CLKDM_CAN_HWSUP,
0349 };
0350
0351 static struct clockdomain iss_44xx_clkdm = {
0352     .name         = "iss_clkdm",
0353     .pwrdm        = { .name = "cam_pwrdm" },
0354     .prcm_partition   = OMAP4430_CM2_PARTITION,
0355     .cm_inst      = OMAP4430_CM2_CAM_INST,
0356     .clkdm_offs   = OMAP4430_CM2_CAM_CAM_CDOFFS,
0357     .wkdep_srcs   = iss_wkup_sleep_deps,
0358     .sleepdep_srcs    = iss_wkup_sleep_deps,
0359     .flags        = CLKDM_CAN_SWSUP,
0360 };
0361
0362 static struct clockdomain l3_dss_44xx_clkdm = {
0363     .name         = "l3_dss_clkdm",
0364     .pwrdm        = { .name = "dss_pwrdm" },
0365     .prcm_partition   = OMAP4430_CM2_PARTITION,
0366     .cm_inst      = OMAP4430_CM2_DSS_INST,
0367     .clkdm_offs   = OMAP4430_CM2_DSS_DSS_CDOFFS,
0368     .dep_bit      = OMAP4430_DSS_STATDEP_SHIFT,
0369     .wkdep_srcs   = l3_dss_wkup_sleep_deps,
0370     .sleepdep_srcs    = l3_dss_wkup_sleep_deps,
0371     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0372 };
0373
0374 static struct clockdomain l4_wkup_44xx_clkdm = {
0375     .name         = "l4_wkup_clkdm",
0376     .pwrdm        = { .name = "wkup_pwrdm" },
0377     .prcm_partition   = OMAP4430_PRM_PARTITION,
0378     .cm_inst      = OMAP4430_PRM_WKUP_CM_INST,
0379     .clkdm_offs   = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
0380     .dep_bit      = OMAP4430_L4WKUP_STATDEP_SHIFT,
0381     .flags        = CLKDM_CAN_HWSUP | CLKDM_ACTIVE_WITH_MPU,
0382 };
0383
0384 static struct clockdomain emu_sys_44xx_clkdm = {
0385     .name         = "emu_sys_clkdm",
0386     .pwrdm        = { .name = "emu_pwrdm" },
0387     .prcm_partition   = OMAP4430_PRM_PARTITION,
0388     .cm_inst      = OMAP4430_PRM_EMU_CM_INST,
0389     .clkdm_offs   = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
0390     .flags        = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP |
0391                  CLKDM_MISSING_IDLE_REPORTING),
0392 };
0393
0394 static struct clockdomain l3_dma_44xx_clkdm = {
0395     .name         = "l3_dma_clkdm",
0396     .pwrdm        = { .name = "core_pwrdm" },
0397     .prcm_partition   = OMAP4430_CM2_PARTITION,
0398     .cm_inst      = OMAP4430_CM2_CORE_INST,
0399     .clkdm_offs   = OMAP4430_CM2_CORE_SDMA_CDOFFS,
0400     .wkdep_srcs   = l3_dma_wkup_sleep_deps,
0401     .sleepdep_srcs    = l3_dma_wkup_sleep_deps,
0402     .flags        = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
0403 };
0404
0405 /* As clockdomains are added or removed above, this list must also be changed */
0406 static struct clockdomain *clockdomains_omap44xx[] __initdata = {
0407     &l4_cefuse_44xx_clkdm,
0408     &l4_cfg_44xx_clkdm,
0409     &tesla_44xx_clkdm,
0410     &l3_gfx_44xx_clkdm,
0411     &ivahd_44xx_clkdm,
0412     &l4_secure_44xx_clkdm,
0413     &l4_per_44xx_clkdm,
0414     &abe_44xx_clkdm,
0415     &l3_instr_44xx_clkdm,
0416     &l3_init_44xx_clkdm,
0417     &d2d_44xx_clkdm,
0418     &mpu0_44xx_clkdm,
0419     &mpu1_44xx_clkdm,
0420     &l3_emif_44xx_clkdm,
0421     &l4_ao_44xx_clkdm,
0422     &ducati_44xx_clkdm,
0423     &mpu_44xx_clkdm,
0424     &l3_2_44xx_clkdm,
0425     &l3_1_44xx_clkdm,
0426     &iss_44xx_clkdm,
0427     &l3_dss_44xx_clkdm,
0428     &l4_wkup_44xx_clkdm,
0429     &emu_sys_44xx_clkdm,
0430     &l3_dma_44xx_clkdm,
0431     NULL
0432 };
0433
0434
0435 void __init omap44xx_clockdomains_init(void)
0436 {
0437     clkdm_register_platform_funcs(&omap4_clkdm_operations);
0438     clkdm_register_clkdms(clockdomains_omap44xx);
0439     clkdm_complete_init();
0440 }