arm/mach-omap2/clockdomains43xx_data.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * AM43xx Clock domains framework
0004  *
0005  * Copyright (C) 2013 Texas Instruments, Inc.
0006  */
0007
0008 #include <linux/kernel.h>
0009 #include <linux/io.h>
0010
0011 #include "clockdomain.h"
0012 #include "prcm44xx.h"
0013 #include "prcm43xx.h"
0014
0015 static struct clockdomain l4_cefuse_43xx_clkdm = {
0016     .name         = "l4_cefuse_clkdm",
0017     .pwrdm        = { .name = "cefuse_pwrdm" },
0018     .prcm_partition   = AM43XX_CM_PARTITION,
0019     .cm_inst      = AM43XX_CM_CEFUSE_INST,
0020     .clkdm_offs   = AM43XX_CM_CEFUSE_CEFUSE_CDOFFS,
0021     .flags        = CLKDM_CAN_SWSUP,
0022 };
0023
0024 static struct clockdomain mpu_43xx_clkdm = {
0025     .name         = "mpu_clkdm",
0026     .pwrdm        = { .name = "mpu_pwrdm" },
0027     .prcm_partition   = AM43XX_CM_PARTITION,
0028     .cm_inst      = AM43XX_CM_MPU_INST,
0029     .clkdm_offs   = AM43XX_CM_MPU_MPU_CDOFFS,
0030     .flags        = CLKDM_CAN_HWSUP_SWSUP,
0031 };
0032
0033 static struct clockdomain l4ls_43xx_clkdm = {
0034     .name         = "l4ls_clkdm",
0035     .pwrdm        = { .name = "per_pwrdm" },
0036     .prcm_partition   = AM43XX_CM_PARTITION,
0037     .cm_inst      = AM43XX_CM_PER_INST,
0038     .clkdm_offs   = AM43XX_CM_PER_L4LS_CDOFFS,
0039     .flags        = CLKDM_CAN_SWSUP,
0040 };
0041
0042 static struct clockdomain tamper_43xx_clkdm = {
0043     .name         = "tamper_clkdm",
0044     .pwrdm        = { .name = "tamper_pwrdm" },
0045     .prcm_partition   = AM43XX_CM_PARTITION,
0046     .cm_inst      = AM43XX_CM_TAMPER_INST,
0047     .clkdm_offs   = AM43XX_CM_TAMPER_TAMPER_CDOFFS,
0048     .flags        = CLKDM_CAN_SWSUP,
0049 };
0050
0051 static struct clockdomain l4_rtc_43xx_clkdm = {
0052     .name         = "l4_rtc_clkdm",
0053     .pwrdm        = { .name = "rtc_pwrdm" },
0054     .prcm_partition   = AM43XX_CM_PARTITION,
0055     .cm_inst      = AM43XX_CM_RTC_INST,
0056     .clkdm_offs   = AM43XX_CM_RTC_RTC_CDOFFS,
0057     .flags        = CLKDM_CAN_SWSUP,
0058 };
0059
0060 static struct clockdomain pruss_ocp_43xx_clkdm = {
0061     .name         = "pruss_ocp_clkdm",
0062     .pwrdm        = { .name = "per_pwrdm" },
0063     .prcm_partition   = AM43XX_CM_PARTITION,
0064     .cm_inst      = AM43XX_CM_PER_INST,
0065     .clkdm_offs   = AM43XX_CM_PER_ICSS_CDOFFS,
0066     .flags        = CLKDM_CAN_SWSUP,
0067 };
0068
0069 static struct clockdomain ocpwp_l3_43xx_clkdm = {
0070     .name         = "ocpwp_l3_clkdm",
0071     .pwrdm        = { .name = "per_pwrdm" },
0072     .prcm_partition   = AM43XX_CM_PARTITION,
0073     .cm_inst      = AM43XX_CM_PER_INST,
0074     .clkdm_offs   = AM43XX_CM_PER_OCPWP_L3_CDOFFS,
0075     .flags        = CLKDM_CAN_SWSUP,
0076 };
0077
0078 static struct clockdomain l3s_tsc_43xx_clkdm = {
0079     .name         = "l3s_tsc_clkdm",
0080     .pwrdm        = { .name = "wkup_pwrdm" },
0081     .prcm_partition   = AM43XX_CM_PARTITION,
0082     .cm_inst      = AM43XX_CM_WKUP_INST,
0083     .clkdm_offs   = AM43XX_CM_WKUP_L3S_TSC_CDOFFS,
0084     .flags        = CLKDM_CAN_SWSUP,
0085 };
0086
0087 static struct clockdomain lcdc_43xx_clkdm = {
0088     .name         = "lcdc_clkdm",
0089     .pwrdm        = { .name = "per_pwrdm" },
0090     .prcm_partition   = AM43XX_CM_PARTITION,
0091     .cm_inst      = AM43XX_CM_PER_INST,
0092     .clkdm_offs   = AM43XX_CM_PER_LCDC_CDOFFS,
0093     .flags        = CLKDM_CAN_SWSUP,
0094 };
0095
0096 static struct clockdomain dss_43xx_clkdm = {
0097     .name         = "dss_clkdm",
0098     .pwrdm        = { .name = "per_pwrdm" },
0099     .prcm_partition   = AM43XX_CM_PARTITION,
0100     .cm_inst      = AM43XX_CM_PER_INST,
0101     .clkdm_offs   = AM43XX_CM_PER_DSS_CDOFFS,
0102     .flags        = CLKDM_CAN_SWSUP,
0103 };
0104
0105 static struct clockdomain l3_aon_43xx_clkdm = {
0106     .name         = "l3_aon_clkdm",
0107     .pwrdm        = { .name = "wkup_pwrdm" },
0108     .prcm_partition   = AM43XX_CM_PARTITION,
0109     .cm_inst      = AM43XX_CM_WKUP_INST,
0110     .clkdm_offs   = AM43XX_CM_WKUP_L3_AON_CDOFFS,
0111     .flags        = CLKDM_CAN_SWSUP,
0112 };
0113
0114 static struct clockdomain emif_43xx_clkdm = {
0115     .name         = "emif_clkdm",
0116     .pwrdm        = { .name = "per_pwrdm" },
0117     .prcm_partition   = AM43XX_CM_PARTITION,
0118     .cm_inst      = AM43XX_CM_PER_INST,
0119     .clkdm_offs   = AM43XX_CM_PER_EMIF_CDOFFS,
0120     .flags        = CLKDM_CAN_SWSUP,
0121 };
0122
0123 static struct clockdomain l4_wkup_aon_43xx_clkdm = {
0124     .name         = "l4_wkup_aon_clkdm",
0125     .pwrdm        = { .name = "wkup_pwrdm" },
0126     .prcm_partition   = AM43XX_CM_PARTITION,
0127     .cm_inst      = AM43XX_CM_WKUP_INST,
0128     .clkdm_offs   = AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS,
0129 };
0130
0131 static struct clockdomain l3_43xx_clkdm = {
0132     .name         = "l3_clkdm",
0133     .pwrdm        = { .name = "per_pwrdm" },
0134     .prcm_partition   = AM43XX_CM_PARTITION,
0135     .cm_inst      = AM43XX_CM_PER_INST,
0136     .clkdm_offs   = AM43XX_CM_PER_L3_CDOFFS,
0137     .flags        = CLKDM_CAN_SWSUP,
0138 };
0139
0140 static struct clockdomain l4_wkup_43xx_clkdm = {
0141     .name         = "l4_wkup_clkdm",
0142     .pwrdm        = { .name = "wkup_pwrdm" },
0143     .prcm_partition   = AM43XX_CM_PARTITION,
0144     .cm_inst      = AM43XX_CM_WKUP_INST,
0145     .clkdm_offs   = AM43XX_CM_WKUP_WKUP_CDOFFS,
0146     .flags        = CLKDM_CAN_SWSUP,
0147 };
0148
0149 static struct clockdomain cpsw_125mhz_43xx_clkdm = {
0150     .name         = "cpsw_125mhz_clkdm",
0151     .pwrdm        = { .name = "per_pwrdm" },
0152     .prcm_partition   = AM43XX_CM_PARTITION,
0153     .cm_inst      = AM43XX_CM_PER_INST,
0154     .clkdm_offs   = AM43XX_CM_PER_CPSW_CDOFFS,
0155     .flags        = CLKDM_CAN_SWSUP,
0156 };
0157
0158 static struct clockdomain gfx_l3_43xx_clkdm = {
0159     .name         = "gfx_l3_clkdm",
0160     .pwrdm        = { .name = "gfx_pwrdm" },
0161     .prcm_partition   = AM43XX_CM_PARTITION,
0162     .cm_inst      = AM43XX_CM_GFX_INST,
0163     .clkdm_offs   = AM43XX_CM_GFX_GFX_L3_CDOFFS,
0164     .flags        = CLKDM_CAN_SWSUP,
0165 };
0166
0167 static struct clockdomain l3s_43xx_clkdm = {
0168     .name         = "l3s_clkdm",
0169     .pwrdm        = { .name = "per_pwrdm" },
0170     .prcm_partition   = AM43XX_CM_PARTITION,
0171     .cm_inst      = AM43XX_CM_PER_INST,
0172     .clkdm_offs   = AM43XX_CM_PER_L3S_CDOFFS,
0173     .flags        = CLKDM_CAN_SWSUP,
0174 };
0175
0176 static struct clockdomain *clockdomains_am43xx[] __initdata = {
0177     &l4_cefuse_43xx_clkdm,
0178     &mpu_43xx_clkdm,
0179     &l4ls_43xx_clkdm,
0180     &tamper_43xx_clkdm,
0181     &l4_rtc_43xx_clkdm,
0182     &pruss_ocp_43xx_clkdm,
0183     &ocpwp_l3_43xx_clkdm,
0184     &l3s_tsc_43xx_clkdm,
0185     &lcdc_43xx_clkdm,
0186     &dss_43xx_clkdm,
0187     &l3_aon_43xx_clkdm,
0188     &emif_43xx_clkdm,
0189     &l4_wkup_aon_43xx_clkdm,
0190     &l3_43xx_clkdm,
0191     &l4_wkup_43xx_clkdm,
0192     &cpsw_125mhz_43xx_clkdm,
0193     &gfx_l3_43xx_clkdm,
0194     &l3s_43xx_clkdm,
0195     NULL
0196 };
0197
0198 void __init am43xx_clockdomains_init(void)
0199 {
0200     clkdm_register_platform_funcs(&am43xx_clkdm_operations);
0201     clkdm_register_clkdms(clockdomains_am43xx);
0202     clkdm_complete_init();
0203 }