arm/mach-omap2/clockdomains33xx_data.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * AM33XX Clock Domain data.
0004  *
0005  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
0006  * Vaibhav Hiremath <hvaibhav@ti.com>
0007  */
0008
0009 #include <linux/kernel.h>
0010 #include <linux/io.h>
0011
0012 #include "clockdomain.h"
0013 #include "cm.h"
0014 #include "cm33xx.h"
0015 #include "cm-regbits-33xx.h"
0016
0017 static struct clockdomain l4ls_am33xx_clkdm = {
0018     .name       = "l4ls_clkdm",
0019     .pwrdm      = { .name = "per_pwrdm" },
0020     .cm_inst    = AM33XX_CM_PER_MOD,
0021     .clkdm_offs = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET,
0022     .flags      = CLKDM_CAN_SWSUP,
0023 };
0024
0025 static struct clockdomain l3s_am33xx_clkdm = {
0026     .name       = "l3s_clkdm",
0027     .pwrdm      = { .name = "per_pwrdm" },
0028     .cm_inst    = AM33XX_CM_PER_MOD,
0029     .clkdm_offs = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET,
0030     .flags      = CLKDM_CAN_SWSUP,
0031 };
0032
0033 static struct clockdomain l4fw_am33xx_clkdm = {
0034     .name       = "l4fw_clkdm",
0035     .pwrdm      = { .name = "per_pwrdm" },
0036     .cm_inst    = AM33XX_CM_PER_MOD,
0037     .clkdm_offs = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET,
0038     .flags      = CLKDM_CAN_SWSUP,
0039 };
0040
0041 static struct clockdomain l3_am33xx_clkdm = {
0042     .name       = "l3_clkdm",
0043     .pwrdm      = { .name = "per_pwrdm" },
0044     .cm_inst    = AM33XX_CM_PER_MOD,
0045     .clkdm_offs = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET,
0046     .flags      = CLKDM_CAN_SWSUP,
0047 };
0048
0049 static struct clockdomain l4hs_am33xx_clkdm = {
0050     .name       = "l4hs_clkdm",
0051     .pwrdm      = { .name = "per_pwrdm" },
0052     .cm_inst    = AM33XX_CM_PER_MOD,
0053     .clkdm_offs = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET,
0054     .flags      = CLKDM_CAN_SWSUP,
0055 };
0056
0057 static struct clockdomain ocpwp_l3_am33xx_clkdm = {
0058     .name       = "ocpwp_l3_clkdm",
0059     .pwrdm      = { .name = "per_pwrdm" },
0060     .cm_inst    = AM33XX_CM_PER_MOD,
0061     .clkdm_offs = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET,
0062     .flags      = CLKDM_CAN_SWSUP,
0063 };
0064
0065 static struct clockdomain pruss_ocp_am33xx_clkdm = {
0066     .name       = "pruss_ocp_clkdm",
0067     .pwrdm      = { .name = "per_pwrdm" },
0068     .cm_inst    = AM33XX_CM_PER_MOD,
0069     .clkdm_offs = AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET,
0070     .flags      = CLKDM_CAN_SWSUP,
0071 };
0072
0073 static struct clockdomain cpsw_125mhz_am33xx_clkdm = {
0074     .name       = "cpsw_125mhz_clkdm",
0075     .pwrdm      = { .name = "per_pwrdm" },
0076     .cm_inst    = AM33XX_CM_PER_MOD,
0077     .clkdm_offs = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET,
0078     .flags      = CLKDM_CAN_SWSUP,
0079 };
0080
0081 static struct clockdomain lcdc_am33xx_clkdm = {
0082     .name       = "lcdc_clkdm",
0083     .pwrdm      = { .name = "per_pwrdm" },
0084     .cm_inst    = AM33XX_CM_PER_MOD,
0085     .clkdm_offs = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET,
0086     .flags      = CLKDM_CAN_SWSUP,
0087 };
0088
0089 static struct clockdomain clk_24mhz_am33xx_clkdm = {
0090     .name       = "clk_24mhz_clkdm",
0091     .pwrdm      = { .name = "per_pwrdm" },
0092     .cm_inst    = AM33XX_CM_PER_MOD,
0093     .clkdm_offs = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET,
0094     .flags      = CLKDM_CAN_SWSUP,
0095 };
0096
0097 static struct clockdomain l4_wkup_am33xx_clkdm = {
0098     .name       = "l4_wkup_clkdm",
0099     .pwrdm      = { .name = "wkup_pwrdm" },
0100     .cm_inst    = AM33XX_CM_WKUP_MOD,
0101     .clkdm_offs = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET,
0102     .flags      = CLKDM_CAN_SWSUP,
0103 };
0104
0105 static struct clockdomain l3_aon_am33xx_clkdm = {
0106     .name       = "l3_aon_clkdm",
0107     .pwrdm      = { .name = "wkup_pwrdm" },
0108     .cm_inst    = AM33XX_CM_WKUP_MOD,
0109     .clkdm_offs = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET,
0110     .flags      = CLKDM_CAN_SWSUP,
0111 };
0112
0113 static struct clockdomain l4_wkup_aon_am33xx_clkdm = {
0114     .name       = "l4_wkup_aon_clkdm",
0115     .pwrdm      = { .name = "wkup_pwrdm" },
0116     .cm_inst    = AM33XX_CM_WKUP_MOD,
0117     .clkdm_offs = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET,
0118     .flags      = CLKDM_CAN_SWSUP,
0119 };
0120
0121 static struct clockdomain mpu_am33xx_clkdm = {
0122     .name       = "mpu_clkdm",
0123     .pwrdm      = { .name = "mpu_pwrdm" },
0124     .cm_inst    = AM33XX_CM_MPU_MOD,
0125     .clkdm_offs = AM33XX_CM_MPU_CLKSTCTRL_OFFSET,
0126     .flags      = CLKDM_CAN_SWSUP,
0127 };
0128
0129 static struct clockdomain l4_rtc_am33xx_clkdm = {
0130     .name       = "l4_rtc_clkdm",
0131     .pwrdm      = { .name = "rtc_pwrdm" },
0132     .cm_inst    = AM33XX_CM_RTC_MOD,
0133     .clkdm_offs = AM33XX_CM_RTC_CLKSTCTRL_OFFSET,
0134     .flags      = CLKDM_CAN_SWSUP,
0135 };
0136
0137 static struct clockdomain gfx_l3_am33xx_clkdm = {
0138     .name       = "gfx_l3_clkdm",
0139     .pwrdm      = { .name = "gfx_pwrdm" },
0140     .cm_inst    = AM33XX_CM_GFX_MOD,
0141     .clkdm_offs = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET,
0142     .flags      = CLKDM_CAN_SWSUP,
0143 };
0144
0145 static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = {
0146     .name       = "gfx_l4ls_gfx_clkdm",
0147     .pwrdm      = { .name = "gfx_pwrdm" },
0148     .cm_inst    = AM33XX_CM_GFX_MOD,
0149     .clkdm_offs = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET,
0150     .flags      = CLKDM_CAN_SWSUP,
0151 };
0152
0153 static struct clockdomain l4_cefuse_am33xx_clkdm = {
0154     .name       = "l4_cefuse_clkdm",
0155     .pwrdm      = { .name = "cefuse_pwrdm" },
0156     .cm_inst    = AM33XX_CM_CEFUSE_MOD,
0157     .clkdm_offs = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET,
0158     .flags      = CLKDM_CAN_SWSUP,
0159 };
0160
0161 static struct clockdomain *clockdomains_am33xx[] __initdata = {
0162     &l4ls_am33xx_clkdm,
0163     &l3s_am33xx_clkdm,
0164     &l4fw_am33xx_clkdm,
0165     &l3_am33xx_clkdm,
0166     &l4hs_am33xx_clkdm,
0167     &ocpwp_l3_am33xx_clkdm,
0168     &pruss_ocp_am33xx_clkdm,
0169     &cpsw_125mhz_am33xx_clkdm,
0170     &lcdc_am33xx_clkdm,
0171     &clk_24mhz_am33xx_clkdm,
0172     &l4_wkup_am33xx_clkdm,
0173     &l3_aon_am33xx_clkdm,
0174     &l4_wkup_aon_am33xx_clkdm,
0175     &mpu_am33xx_clkdm,
0176     &l4_rtc_am33xx_clkdm,
0177     &gfx_l3_am33xx_clkdm,
0178     &gfx_l4ls_gfx_am33xx_clkdm,
0179     &l4_cefuse_am33xx_clkdm,
0180     NULL,
0181 };
0182
0183 void __init am33xx_clockdomains_init(void)
0184 {
0185     clkdm_register_platform_funcs(&am33xx_clkdm_operations);
0186     clkdm_register_clkdms(clockdomains_am33xx);
0187     clkdm_complete_init();
0188 }