arm/mach-omap2/clockdomains2430_data.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * OMAP2xxx clockdomains
0004  *
0005  * Copyright (C) 2008-2009 Texas Instruments, Inc.
0006  * Copyright (C) 2008-2010 Nokia Corporation
0007  *
0008  * Paul Walmsley, Jouni Högander
0009  *
0010  * This file contains clockdomains and clockdomain wakeup dependencies
0011  * for OMAP2xxx chips.  Some notes:
0012  *
0013  * A useful validation rule for struct clockdomain: Any clockdomain
0014  * referenced by a wkdep_srcs must have a dep_bit assigned.  So
0015  * wkdep_srcs are really just software-controllable dependencies.
0016  * Non-software-controllable dependencies do exist, but they are not
0017  * encoded below (yet).
0018  *
0019  * 24xx does not support programmable sleep dependencies (SLEEPDEP)
0020  *
0021  * The overly-specific dep_bit names are due to a bit name collision
0022  * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
0023  * value are the same for all powerdomains: 2
0024  *
0025  * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
0026  * sanity check?
0027  * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
0028  */
0029
0030 /*
0031  * To-Do List
0032  * -> Port the Sleep/Wakeup dependencies for the domains
0033  *    from the Power domain framework
0034  */
0035
0036 #include <linux/kernel.h>
0037 #include <linux/io.h>
0038
0039 #include "soc.h"
0040 #include "clockdomain.h"
0041 #include "prm2xxx_3xxx.h"
0042 #include "cm2xxx_3xxx.h"
0043 #include "cm-regbits-24xx.h"
0044 #include "prm-regbits-24xx.h"
0045
0046 /*
0047  * Clockdomain dependencies for wkdeps
0048  *
0049  * XXX Hardware dependencies (e.g., dependencies that cannot be
0050  * changed in software) are not included here yet, but should be.
0051  */
0052
0053 /* Wakeup dependency source arrays */
0054
0055 /* 2430-specific possible wakeup dependencies */
0056
0057 /* 2430 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP, MDM */
0058 static struct clkdm_dep core_2430_wkdeps[] = {
0059     { .clkdm_name = "dsp_clkdm" },
0060     { .clkdm_name = "gfx_clkdm" },
0061     { .clkdm_name = "mpu_clkdm" },
0062     { .clkdm_name = "wkup_clkdm" },
0063     { .clkdm_name = "mdm_clkdm" },
0064     { NULL },
0065 };
0066
0067 /* 2430 PM_WKDEP_MPU: CORE, DSP, WKUP, MDM */
0068 static struct clkdm_dep mpu_2430_wkdeps[] = {
0069     { .clkdm_name = "core_l3_clkdm" },
0070     { .clkdm_name = "core_l4_clkdm" },
0071     { .clkdm_name = "dsp_clkdm" },
0072     { .clkdm_name = "wkup_clkdm" },
0073     { .clkdm_name = "mdm_clkdm" },
0074     { NULL },
0075 };
0076
0077 /* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
0078 static struct clkdm_dep mdm_2430_wkdeps[] = {
0079     { .clkdm_name = "core_l3_clkdm" },
0080     { .clkdm_name = "core_l4_clkdm" },
0081     { .clkdm_name = "mpu_clkdm" },
0082     { .clkdm_name = "wkup_clkdm" },
0083     { NULL },
0084 };
0085
0086 /*
0087  * 2430-only clockdomains
0088  */
0089
0090 static struct clockdomain mpu_2430_clkdm = {
0091     .name       = "mpu_clkdm",
0092     .pwrdm      = { .name = "mpu_pwrdm" },
0093     .flags      = CLKDM_CAN_HWSUP_SWSUP,
0094     .wkdep_srcs = mpu_2430_wkdeps,
0095     .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
0096 };
0097
0098 /* Another case of bit name collisions between several registers: EN_MDM */
0099 static struct clockdomain mdm_clkdm = {
0100     .name       = "mdm_clkdm",
0101     .pwrdm      = { .name = "mdm_pwrdm" },
0102     .flags      = CLKDM_CAN_HWSUP_SWSUP,
0103     .dep_bit    = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
0104     .wkdep_srcs = mdm_2430_wkdeps,
0105     .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
0106 };
0107
0108 static struct clockdomain dsp_2430_clkdm = {
0109     .name       = "dsp_clkdm",
0110     .pwrdm      = { .name = "dsp_pwrdm" },
0111     .flags      = CLKDM_CAN_HWSUP_SWSUP,
0112     .dep_bit    = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
0113     .wkdep_srcs = dsp_24xx_wkdeps,
0114     .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
0115 };
0116
0117 static struct clockdomain gfx_2430_clkdm = {
0118     .name       = "gfx_clkdm",
0119     .pwrdm      = { .name = "gfx_pwrdm" },
0120     .flags      = CLKDM_CAN_HWSUP_SWSUP,
0121     .wkdep_srcs = gfx_24xx_wkdeps,
0122     .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
0123 };
0124
0125 /*
0126  * XXX add usecounting for clkdm dependencies, otherwise the presence
0127  * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
0128  * could cause trouble
0129  */
0130 static struct clockdomain core_l3_2430_clkdm = {
0131     .name       = "core_l3_clkdm",
0132     .pwrdm      = { .name = "core_pwrdm" },
0133     .flags      = CLKDM_CAN_HWSUP,
0134     .dep_bit    = OMAP24XX_EN_CORE_SHIFT,
0135     .wkdep_srcs = core_2430_wkdeps,
0136     .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
0137 };
0138
0139 /*
0140  * XXX add usecounting for clkdm dependencies, otherwise the presence
0141  * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
0142  * could cause trouble
0143  */
0144 static struct clockdomain core_l4_2430_clkdm = {
0145     .name       = "core_l4_clkdm",
0146     .pwrdm      = { .name = "core_pwrdm" },
0147     .flags      = CLKDM_CAN_HWSUP,
0148     .dep_bit    = OMAP24XX_EN_CORE_SHIFT,
0149     .wkdep_srcs = core_2430_wkdeps,
0150     .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
0151 };
0152
0153 static struct clockdomain dss_2430_clkdm = {
0154     .name       = "dss_clkdm",
0155     .pwrdm      = { .name = "core_pwrdm" },
0156     .flags      = CLKDM_CAN_HWSUP,
0157     .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
0158 };
0159
0160 static struct clockdomain *clockdomains_omap243x[] __initdata = {
0161     &wkup_common_clkdm,
0162     &mpu_2430_clkdm,
0163     &mdm_clkdm,
0164     &dsp_2430_clkdm,
0165     &gfx_2430_clkdm,
0166     &core_l3_2430_clkdm,
0167     &core_l4_2430_clkdm,
0168     &dss_2430_clkdm,
0169     NULL,
0170 };
0171
0172 void __init omap243x_clockdomains_init(void)
0173 {
0174     if (!cpu_is_omap243x())
0175         return;
0176
0177     clkdm_register_platform_funcs(&omap2_clkdm_operations);
0178     clkdm_register_clkdms(clockdomains_omap243x);
0179     clkdm_complete_init();
0180 }
0181