arm/mach-omap2/clockdomains2420_data.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * OMAP2420 clockdomains
0004  *
0005  * Copyright (C) 2008-2011 Texas Instruments, Inc.
0006  * Copyright (C) 2008-2010 Nokia Corporation
0007  *
0008  * Paul Walmsley, Jouni Högander
0009  *
0010  * This file contains clockdomains and clockdomain wakeup dependencies
0011  * for OMAP2420 chips.  Some notes:
0012  *
0013  * A useful validation rule for struct clockdomain: Any clockdomain
0014  * referenced by a wkdep_srcs must have a dep_bit assigned.  So
0015  * wkdep_srcs are really just software-controllable dependencies.
0016  * Non-software-controllable dependencies do exist, but they are not
0017  * encoded below (yet).
0018  *
0019  * 24xx does not support programmable sleep dependencies (SLEEPDEP)
0020  *
0021  * The overly-specific dep_bit names are due to a bit name collision
0022  * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
0023  * value are the same for all powerdomains: 2
0024  *
0025  * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
0026  * sanity check?
0027  * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
0028  */
0029
0030 /*
0031  * To-Do List
0032  * -> Port the Sleep/Wakeup dependencies for the domains
0033  *    from the Power domain framework
0034  */
0035
0036 #include <linux/kernel.h>
0037 #include <linux/io.h>
0038
0039 #include "soc.h"
0040 #include "clockdomain.h"
0041 #include "prm2xxx_3xxx.h"
0042 #include "cm2xxx_3xxx.h"
0043 #include "cm-regbits-24xx.h"
0044 #include "prm-regbits-24xx.h"
0045
0046 /*
0047  * Clockdomain dependencies for wkdeps
0048  *
0049  * XXX Hardware dependencies (e.g., dependencies that cannot be
0050  * changed in software) are not included here yet, but should be.
0051  */
0052
0053 /* Wakeup dependency source arrays */
0054
0055 /* 2420-specific possible wakeup dependencies */
0056
0057 /* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP */
0058 static struct clkdm_dep mpu_2420_wkdeps[] = {
0059     { .clkdm_name = "core_l3_clkdm" },
0060     { .clkdm_name = "core_l4_clkdm" },
0061     { .clkdm_name = "dsp_clkdm" },
0062     { .clkdm_name = "wkup_clkdm" },
0063     { NULL },
0064 };
0065
0066 /* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP */
0067 static struct clkdm_dep core_2420_wkdeps[] = {
0068     { .clkdm_name = "dsp_clkdm" },
0069     { .clkdm_name = "gfx_clkdm" },
0070     { .clkdm_name = "mpu_clkdm" },
0071     { .clkdm_name = "wkup_clkdm" },
0072     { NULL },
0073 };
0074
0075 /*
0076  * 2420-only clockdomains
0077  */
0078
0079 static struct clockdomain mpu_2420_clkdm = {
0080     .name       = "mpu_clkdm",
0081     .pwrdm      = { .name = "mpu_pwrdm" },
0082     .flags      = CLKDM_CAN_HWSUP,
0083     .wkdep_srcs = mpu_2420_wkdeps,
0084     .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
0085 };
0086
0087 static struct clockdomain iva1_2420_clkdm = {
0088     .name       = "iva1_clkdm",
0089     .pwrdm      = { .name = "dsp_pwrdm" },
0090     .flags      = CLKDM_CAN_HWSUP_SWSUP,
0091     .dep_bit    = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
0092     .wkdep_srcs = dsp_24xx_wkdeps,
0093     .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
0094 };
0095
0096 static struct clockdomain dsp_2420_clkdm = {
0097     .name       = "dsp_clkdm",
0098     .pwrdm      = { .name = "dsp_pwrdm" },
0099     .flags      = CLKDM_CAN_HWSUP_SWSUP,
0100     .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
0101 };
0102
0103 static struct clockdomain gfx_2420_clkdm = {
0104     .name       = "gfx_clkdm",
0105     .pwrdm      = { .name = "gfx_pwrdm" },
0106     .flags      = CLKDM_CAN_HWSUP_SWSUP,
0107     .wkdep_srcs = gfx_24xx_wkdeps,
0108     .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
0109 };
0110
0111 static struct clockdomain core_l3_2420_clkdm = {
0112     .name       = "core_l3_clkdm",
0113     .pwrdm      = { .name = "core_pwrdm" },
0114     .flags      = CLKDM_CAN_HWSUP,
0115     .wkdep_srcs = core_2420_wkdeps,
0116     .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
0117 };
0118
0119 static struct clockdomain core_l4_2420_clkdm = {
0120     .name       = "core_l4_clkdm",
0121     .pwrdm      = { .name = "core_pwrdm" },
0122     .flags      = CLKDM_CAN_HWSUP,
0123     .wkdep_srcs = core_2420_wkdeps,
0124     .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
0125 };
0126
0127 static struct clockdomain dss_2420_clkdm = {
0128     .name       = "dss_clkdm",
0129     .pwrdm      = { .name = "core_pwrdm" },
0130     .flags      = CLKDM_CAN_HWSUP,
0131     .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
0132 };
0133
0134 static struct clockdomain *clockdomains_omap242x[] __initdata = {
0135     &wkup_common_clkdm,
0136     &mpu_2420_clkdm,
0137     &iva1_2420_clkdm,
0138     &dsp_2420_clkdm,
0139     &gfx_2420_clkdm,
0140     &core_l3_2420_clkdm,
0141     &core_l4_2420_clkdm,
0142     &dss_2420_clkdm,
0143     NULL,
0144 };
0145
0146 void __init omap242x_clockdomains_init(void)
0147 {
0148     if (!cpu_is_omap242x())
0149         return;
0150
0151     clkdm_register_platform_funcs(&omap2_clkdm_operations);
0152     clkdm_register_clkdms(clockdomains_omap242x);
0153     clkdm_complete_init();
0154 }