arm/mach-omap2/clock.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  linux/arch/arm/mach-omap2/clock.h
0004  *
0005  *  Copyright (C) 2005-2009 Texas Instruments, Inc.
0006  *  Copyright (C) 2004-2011 Nokia Corporation
0007  *
0008  *  Contacts:
0009  *  Richard Woodruff <r-woodruff2@ti.com>
0010  *  Paul Walmsley
0011  */
0012
0013 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
0014 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
0015
0016 #include <linux/kernel.h>
0017 #include <linux/list.h>
0018
0019 #include <linux/clkdev.h>
0020 #include <linux/clk-provider.h>
0021 #include <linux/clk/ti.h>
0022
0023 /* struct clksel_rate.flags possibilities */
0024 #define RATE_IN_242X        (1 << 0)
0025 #define RATE_IN_243X        (1 << 1)
0026 #define RATE_IN_3430ES1     (1 << 2)    /* 3430ES1 rates only */
0027 #define RATE_IN_3430ES2PLUS (1 << 3)    /* 3430 ES >= 2 rates only */
0028 #define RATE_IN_36XX        (1 << 4)
0029 #define RATE_IN_4430        (1 << 5)
0030 #define RATE_IN_TI816X      (1 << 6)
0031 #define RATE_IN_4460        (1 << 7)
0032 #define RATE_IN_AM33XX      (1 << 8)
0033 #define RATE_IN_TI814X      (1 << 9)
0034
0035 #define RATE_IN_24XX        (RATE_IN_242X | RATE_IN_243X)
0036 #define RATE_IN_34XX        (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
0037 #define RATE_IN_3XXX        (RATE_IN_34XX | RATE_IN_36XX)
0038 #define RATE_IN_44XX        (RATE_IN_4430 | RATE_IN_4460)
0039
0040 /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
0041 #define RATE_IN_3430ES2PLUS_36XX    (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
0042
0043 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
0044 #define CORE_CLK_SRC_32K        0x0
0045 #define CORE_CLK_SRC_DPLL       0x1
0046 #define CORE_CLK_SRC_DPLL_X2        0x2
0047
0048 /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
0049 #define OMAP2XXX_EN_DPLL_LPBYPASS       0x1
0050 #define OMAP2XXX_EN_DPLL_FRBYPASS       0x2
0051 #define OMAP2XXX_EN_DPLL_LOCKED         0x3
0052
0053 /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
0054 #define OMAP3XXX_EN_DPLL_LPBYPASS       0x5
0055 #define OMAP3XXX_EN_DPLL_FRBYPASS       0x6
0056 #define OMAP3XXX_EN_DPLL_LOCKED         0x7
0057
0058 /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
0059 #define OMAP4XXX_EN_DPLL_MNBYPASS       0x4
0060 #define OMAP4XXX_EN_DPLL_LPBYPASS       0x5
0061 #define OMAP4XXX_EN_DPLL_FRBYPASS       0x6
0062 #define OMAP4XXX_EN_DPLL_LOCKED         0x7
0063
0064 extern struct ti_clk_ll_ops omap_clk_ll_ops;
0065
0066 extern u16 cpu_mask;
0067
0068 extern const struct clkops clkops_omap2_dflt_wait;
0069 extern const struct clkops clkops_omap2_dflt;
0070
0071 extern struct clk_functions omap2_clk_functions;
0072
0073 int __init omap2_clk_setup_ll_ops(void);
0074
0075 void __init ti_clk_init_features(void);
0076 #endif