arm/mach-omap2/clock.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/arch/arm/mach-omap2/clock.c
0004  *
0005  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
0006  *  Copyright (C) 2004-2010 Nokia Corporation
0007  *
0008  *  Contacts:
0009  *  Richard Woodruff <r-woodruff2@ti.com>
0010  *  Paul Walmsley
0011  */
0012 #undef DEBUG
0013
0014 #include <linux/kernel.h>
0015 #include <linux/export.h>
0016 #include <linux/list.h>
0017 #include <linux/errno.h>
0018 #include <linux/err.h>
0019 #include <linux/delay.h>
0020 #include <linux/clk.h>
0021 #include <linux/clk-provider.h>
0022 #include <linux/io.h>
0023 #include <linux/bitops.h>
0024 #include <linux/of_address.h>
0025 #include <asm/cpu.h>
0026
0027 #include <trace/events/power.h>
0028
0029 #include "soc.h"
0030 #include "clockdomain.h"
0031 #include "clock.h"
0032 #include "cm.h"
0033 #include "cm2xxx.h"
0034 #include "cm3xxx.h"
0035 #include "cm-regbits-24xx.h"
0036 #include "cm-regbits-34xx.h"
0037 #include "common.h"
0038
0039 u16 cpu_mask;
0040
0041 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
0042 #define OMAP3430_DPLL_FINT_BAND1_MIN    750000
0043 #define OMAP3430_DPLL_FINT_BAND1_MAX    2100000
0044 #define OMAP3430_DPLL_FINT_BAND2_MIN    7500000
0045 #define OMAP3430_DPLL_FINT_BAND2_MAX    21000000
0046
0047 /*
0048  * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
0049  * From device data manual section 4.3 "DPLL and DLL Specifications".
0050  */
0051 #define OMAP3PLUS_DPLL_FINT_MIN     32000
0052 #define OMAP3PLUS_DPLL_FINT_MAX     52000000
0053
0054 struct ti_clk_ll_ops omap_clk_ll_ops = {
0055     .clkdm_clk_enable = clkdm_clk_enable,
0056     .clkdm_clk_disable = clkdm_clk_disable,
0057     .clkdm_lookup = clkdm_lookup,
0058     .cm_wait_module_ready = omap_cm_wait_module_ready,
0059     .cm_split_idlest_reg = cm_split_idlest_reg,
0060 };
0061
0062 /**
0063  * omap2_clk_setup_ll_ops - setup clock driver low-level ops
0064  *
0065  * Sets up clock driver low-level platform ops. These are needed
0066  * for register accesses and various other misc platform operations.
0067  * Returns 0 on success, -EBUSY if low level ops have been registered
0068  * already.
0069  */
0070 int __init omap2_clk_setup_ll_ops(void)
0071 {
0072     return ti_clk_setup_ll_ops(&omap_clk_ll_ops);
0073 }
0074
0075 /*
0076  * OMAP2+ specific clock functions
0077  */
0078
0079 /**
0080  * ti_clk_init_features - init clock features struct for the SoC
0081  *
0082  * Initializes the clock features struct based on the SoC type.
0083  */
0084 void __init ti_clk_init_features(void)
0085 {
0086     struct ti_clk_features features = { 0 };
0087     /* Fint setup for DPLLs */
0088     if (cpu_is_omap3430()) {
0089         features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
0090         features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
0091         features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
0092         features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
0093     } else {
0094         features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
0095         features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
0096     }
0097
0098     /* Bypass value setup for DPLLs */
0099     if (cpu_is_omap24xx()) {
0100         features.dpll_bypass_vals |=
0101             (1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
0102             (1 << OMAP2XXX_EN_DPLL_FRBYPASS);
0103     } else if (cpu_is_omap34xx()) {
0104         features.dpll_bypass_vals |=
0105             (1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
0106             (1 << OMAP3XXX_EN_DPLL_FRBYPASS);
0107     } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
0108            soc_is_omap54xx() || soc_is_dra7xx()) {
0109         features.dpll_bypass_vals |=
0110             (1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
0111             (1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
0112             (1 << OMAP4XXX_EN_DPLL_MNBYPASS);
0113     }
0114
0115     /* Jitter correction only available on OMAP343X */
0116     if (cpu_is_omap343x())
0117         features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
0118
0119     if (omap_type() == OMAP2_DEVICE_TYPE_GP)
0120         features.flags |= TI_CLK_DEVICE_TYPE_GP;
0121
0122     /* Idlest value for interface clocks.
0123      * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
0124      * 34xx reverses this, just to keep us on our toes
0125      * AM35xx uses both, depending on the module.
0126      */
0127     if (cpu_is_omap24xx())
0128         features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
0129     else if (cpu_is_omap34xx())
0130         features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
0131
0132     /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
0133     if (omap_rev() == OMAP3430_REV_ES1_0)
0134         features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
0135
0136     /* Errata I810 for omap5 / dra7 */
0137     if (soc_is_omap54xx() || soc_is_dra7xx())
0138         features.flags |= TI_CLK_ERRATA_I810;
0139
0140     ti_clk_setup_features(&features);
0141 }