arm/mach-omap1/sram.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * linux/arch/arm/plat-omap/sram-fn.S
0004  *
0005  * Functions that need to be run in internal SRAM
0006  */
0007
0008 #include <linux/linkage.h>
0009 #include <linux/soc/ti/omap1-io.h>
0010
0011 #include <asm/assembler.h>
0012
0013 #include "hardware.h"
0014 #include "iomap.h"
0015
0016     .text
0017
0018 /*
0019  * Reprograms ULPD and CKCTL.
0020  */
0021     .align  3
0022 ENTRY(omap1_sram_reprogram_clock)
0023     stmfd   sp!, {r0 - r12, lr}     @ save registers on stack
0024
0025     mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
0026     orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
0027     orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
0028
0029     mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
0030     orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
0031     orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
0032
0033     tst r0, #1 << 4         @ want lock mode?
0034     beq newck               @ nope
0035     bic r0, r0, #1 << 4         @ else clear lock bit
0036     strh    r0, [r2]            @ set dpll into bypass mode
0037     orr r0, r0, #1 << 4         @ set lock bit again
0038
0039 newck:
0040     strh    r1, [r3]            @ write new ckctl value
0041     strh    r0, [r2]            @ write new dpll value
0042
0043     mov r4, #0x0700         @ let the clocks settle
0044     orr r4, r4, #0x00ff
0045 delay:  sub r4, r4, #1
0046     cmp r4, #0
0047     bne delay
0048
0049 lock:   ldrh    r4, [r2], #0            @ read back dpll value
0050     tst r0, #1 << 4         @ want lock mode?
0051     beq out             @ nope
0052     tst r4, #1 << 0         @ dpll rate locked?
0053     beq lock                @ try again
0054
0055 out:
0056     ldmfd   sp!, {r0 - r12, pc}     @ restore regs and return
0057 ENTRY(omap1_sram_reprogram_clock_sz)
0058     .word   . - omap1_sram_reprogram_clock