arm/mach-omap1/pm.h

0001 /*
0002  * arch/arm/mach-omap1/pm.h
0003  *
0004  * Header file for OMAP1 Power Management Routines
0005  *
0006  * Author: MontaVista Software, Inc.
0007  *     support@mvista.com
0008  *
0009  * Copyright 2002 MontaVista Software Inc.
0010  *
0011  * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
0012  *
0013  * This program is free software; you can redistribute it and/or modify it
0014  * under the terms of the GNU General Public License as published by the
0015  * Free Software Foundation; either version 2 of the License, or (at your
0016  * option) any later version.
0017  *
0018  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
0019  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
0020  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
0021  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
0022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0023  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
0024  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0025  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0026  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0027  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0028  *
0029  * You should have received a copy of the GNU General Public License along
0030  * with this program; if not, write to the Free Software Foundation, Inc.,
0031  * 675 Mass Ave, Cambridge, MA 02139, USA.
0032  */
0033
0034 #ifndef __ARCH_ARM_MACH_OMAP1_PM_H
0035 #define __ARCH_ARM_MACH_OMAP1_PM_H
0036
0037 #include <linux/soc/ti/omap1-io.h>
0038
0039 /*
0040  * ----------------------------------------------------------------------------
0041  * Register and offset definitions to be used in PM assembler code
0042  * ----------------------------------------------------------------------------
0043  */
0044 #define CLKGEN_REG_ASM_BASE     OMAP1_IO_ADDRESS(0xfffece00)
0045 #define ARM_IDLECT1_ASM_OFFSET      0x04
0046 #define ARM_IDLECT2_ASM_OFFSET      0x08
0047
0048 #define TCMIF_ASM_BASE          OMAP1_IO_ADDRESS(0xfffecc00)
0049 #define EMIFS_CONFIG_ASM_OFFSET     0x0c
0050 #define EMIFF_SDRAM_CONFIG_ASM_OFFSET   0x20
0051
0052 /*
0053  * ----------------------------------------------------------------------------
0054  * Power management bitmasks
0055  * ----------------------------------------------------------------------------
0056  */
0057 #define IDLE_WAIT_CYCLES        0x00000fff
0058 #define PERIPHERAL_ENABLE       0x2
0059
0060 #define SELF_REFRESH_MODE       0x0c000001
0061 #define IDLE_EMIFS_REQUEST      0xc
0062 #define MODEM_32K_EN            0x1
0063 #define PER_EN              0x1
0064
0065 #define CPU_SUSPEND_SIZE        200
0066 #define ULPD_LOW_PWR_EN         0x0001
0067 #define ULPD_DEEP_SLEEP_TRANSITION_EN   0x0010
0068 #define ULPD_SETUP_ANALOG_CELL_3_VAL    0
0069 #define ULPD_POWER_CTRL_REG_VAL     0x0219
0070
0071 #define DSP_IDLE_DELAY          10
0072 #define DSP_IDLE            0x0040
0073 #define DSP_RST             0x0004
0074 #define DSP_ENABLE          0x0002
0075 #define SUFFICIENT_DSP_RESET_TIME   1000
0076 #define DEFAULT_MPUI_CONFIG     0x05cf
0077 #define ENABLE_XORCLK           0x2
0078 #define DSP_CLOCK_ENABLE        0x2000
0079 #define DSP_IDLE_MODE           0x2
0080 #define TC_IDLE_REQUEST         (0x0000000c)
0081
0082 #define IRQ_LEVEL2          (1<<0)
0083 #define IRQ_KEYBOARD            (1<<1)
0084 #define IRQ_UART2           (1<<15)
0085
0086 #define PDE_BIT             0x08
0087 #define PWD_EN_BIT          0x04
0088 #define EN_PERCK_BIT            0x04
0089
0090 #define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7
0091 #define OMAP1510_BIG_SLEEP_REQUEST  0x0cc5
0092 #define OMAP1510_IDLE_LOOP_REQUEST  0x0c00
0093 #define OMAP1510_IDLE_CLOCK_DOMAINS 0x2
0094
0095 /* Both big sleep and deep sleep use same values. Difference is in ULPD. */
0096 #define OMAP1610_IDLECT1_SLEEP_VAL  0x13c7
0097 #define OMAP1610_IDLECT2_SLEEP_VAL  0x09c7
0098 #define OMAP1610_IDLECT3_VAL        0x3f
0099 #define OMAP1610_IDLECT3_SLEEP_ORMASK   0x2c
0100 #define OMAP1610_IDLECT3        0xfffece24
0101 #define OMAP1610_IDLE_LOOP_REQUEST  0x0400
0102
0103 #define OMAP7XX_IDLECT1_SLEEP_VAL   0x16c7
0104 #define OMAP7XX_IDLECT2_SLEEP_VAL   0x09c7
0105 #define OMAP7XX_IDLECT3_VAL     0x3f
0106 #define OMAP7XX_IDLECT3     0xfffece24
0107 #define OMAP7XX_IDLE_LOOP_REQUEST   0x0C00
0108
0109 #if     !defined(CONFIG_ARCH_OMAP730) && \
0110     !defined(CONFIG_ARCH_OMAP850) && \
0111     !defined(CONFIG_ARCH_OMAP15XX) && \
0112     !defined(CONFIG_ARCH_OMAP16XX)
0113 #warning "Power management for this processor not implemented yet"
0114 #endif
0115
0116 #ifndef __ASSEMBLER__
0117
0118 #include <linux/clk.h>
0119
0120 extern struct kset power_subsys;
0121
0122 extern void prevent_idle_sleep(void);
0123 extern void allow_idle_sleep(void);
0124
0125 extern void omap1_pm_idle(void);
0126 extern void omap1_pm_suspend(void);
0127
0128 extern void omap7xx_cpu_suspend(unsigned long, unsigned long);
0129 extern void omap1510_cpu_suspend(unsigned long, unsigned long);
0130 extern void omap1610_cpu_suspend(unsigned long, unsigned long);
0131 extern void omap7xx_idle_loop_suspend(void);
0132 extern void omap1510_idle_loop_suspend(void);
0133 extern void omap1610_idle_loop_suspend(void);
0134
0135 extern unsigned int omap7xx_cpu_suspend_sz;
0136 extern unsigned int omap1510_cpu_suspend_sz;
0137 extern unsigned int omap1610_cpu_suspend_sz;
0138 extern unsigned int omap7xx_idle_loop_suspend_sz;
0139 extern unsigned int omap1510_idle_loop_suspend_sz;
0140 extern unsigned int omap1610_idle_loop_suspend_sz;
0141
0142 #ifdef CONFIG_OMAP_SERIAL_WAKE
0143 extern void omap_serial_wake_trigger(int enable);
0144 #else
0145 #define omap_serial_wakeup_init()   {}
0146 #define omap_serial_wake_trigger(x) {}
0147 #endif  /* CONFIG_OMAP_SERIAL_WAKE */
0148
0149 #define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
0150 #define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
0151 #define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
0152
0153 #define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x)
0154 #define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
0155 #define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x]
0156
0157 #define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
0158 #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
0159 #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
0160
0161 #define MPUI7XX_SAVE(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] = omap_readl(x)
0162 #define MPUI7XX_RESTORE(x) omap_writel((mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]), (x))
0163 #define MPUI7XX_SHOW(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]
0164
0165 #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
0166 #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
0167 #define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
0168
0169 #define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
0170 #define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
0171 #define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
0172
0173 /*
0174  * List of global OMAP registers to preserve.
0175  * More ones like CP and general purpose register values are preserved
0176  * with the stack pointer in sleep.S.
0177  */
0178
0179 enum arm_save_state {
0180     ARM_SLEEP_SAVE_START = 0,
0181     /*
0182      * MPU control registers 32 bits
0183      */
0184     ARM_SLEEP_SAVE_ARM_CKCTL,
0185     ARM_SLEEP_SAVE_ARM_IDLECT1,
0186     ARM_SLEEP_SAVE_ARM_IDLECT2,
0187     ARM_SLEEP_SAVE_ARM_IDLECT3,
0188     ARM_SLEEP_SAVE_ARM_EWUPCT,
0189     ARM_SLEEP_SAVE_ARM_RSTCT1,
0190     ARM_SLEEP_SAVE_ARM_RSTCT2,
0191     ARM_SLEEP_SAVE_ARM_SYSST,
0192     ARM_SLEEP_SAVE_SIZE
0193 };
0194
0195 enum dsp_save_state {
0196     DSP_SLEEP_SAVE_START = 0,
0197     /*
0198      * DSP registers 16 bits
0199      */
0200     DSP_SLEEP_SAVE_DSP_IDLECT2,
0201     DSP_SLEEP_SAVE_SIZE
0202 };
0203
0204 enum ulpd_save_state {
0205     ULPD_SLEEP_SAVE_START = 0,
0206     /*
0207      * ULPD registers 16 bits
0208      */
0209     ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
0210     ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
0211     ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
0212     ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
0213     ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
0214     ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
0215     ULPD_SLEEP_SAVE_SIZE
0216 };
0217
0218 enum mpui1510_save_state {
0219     MPUI1510_SLEEP_SAVE_START = 0,
0220     /*
0221      * MPUI registers 32 bits
0222      */
0223     MPUI1510_SLEEP_SAVE_MPUI_CTRL,
0224     MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
0225     MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
0226     MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
0227     MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
0228     MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
0229     MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
0230     MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
0231 #if defined(CONFIG_ARCH_OMAP15XX)
0232     MPUI1510_SLEEP_SAVE_SIZE
0233 #else
0234     MPUI1510_SLEEP_SAVE_SIZE = 0
0235 #endif
0236 };
0237
0238 enum mpui7xx_save_state {
0239     MPUI7XX_SLEEP_SAVE_START = 0,
0240     /*
0241      * MPUI registers 32 bits
0242      */
0243     MPUI7XX_SLEEP_SAVE_MPUI_CTRL,
0244     MPUI7XX_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
0245     MPUI7XX_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
0246     MPUI7XX_SLEEP_SAVE_MPUI_DSP_STATUS,
0247     MPUI7XX_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
0248     MPUI7XX_SLEEP_SAVE_EMIFS_CONFIG,
0249     MPUI7XX_SLEEP_SAVE_OMAP_IH1_MIR,
0250     MPUI7XX_SLEEP_SAVE_OMAP_IH2_0_MIR,
0251     MPUI7XX_SLEEP_SAVE_OMAP_IH2_1_MIR,
0252 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
0253     MPUI7XX_SLEEP_SAVE_SIZE
0254 #else
0255     MPUI7XX_SLEEP_SAVE_SIZE = 0
0256 #endif
0257 };
0258
0259 enum mpui1610_save_state {
0260     MPUI1610_SLEEP_SAVE_START = 0,
0261     /*
0262      * MPUI registers 32 bits
0263      */
0264     MPUI1610_SLEEP_SAVE_MPUI_CTRL,
0265     MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
0266     MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
0267     MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
0268     MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
0269     MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
0270     MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
0271     MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
0272     MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
0273     MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
0274     MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
0275 #if defined(CONFIG_ARCH_OMAP16XX)
0276     MPUI1610_SLEEP_SAVE_SIZE
0277 #else
0278     MPUI1610_SLEEP_SAVE_SIZE = 0
0279 #endif
0280 };
0281
0282 #endif /* ASSEMBLER */
0283 #endif /* __ASM_ARCH_OMAP_PM_H */