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0001 /*
0002  * linux/arch/arm/mach-omap1/pm.c
0003  *
0004  * OMAP Power Management Routines
0005  *
0006  * Original code for the SA11x0:
0007  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
0008  *
0009  * Modified for the PXA250 by Nicolas Pitre:
0010  * Copyright (c) 2002 Monta Vista Software, Inc.
0011  *
0012  * Modified for the OMAP1510 by David Singleton:
0013  * Copyright (c) 2002 Monta Vista Software, Inc.
0014  *
0015  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
0016  *
0017  * This program is free software; you can redistribute it and/or modify it
0018  * under the terms of the GNU General Public License as published by the
0019  * Free Software Foundation; either version 2 of the License, or (at your
0020  * option) any later version.
0021  *
0022  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
0023  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
0024  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
0025  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
0026  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0027  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
0028  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0029  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0030  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0031  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0032  *
0033  * You should have received a copy of the GNU General Public License along
0034  * with this program; if not, write to the Free Software Foundation, Inc.,
0035  * 675 Mass Ave, Cambridge, MA 02139, USA.
0036  */
0037 
0038 #include <linux/suspend.h>
0039 #include <linux/sched.h>
0040 #include <linux/debugfs.h>
0041 #include <linux/seq_file.h>
0042 #include <linux/interrupt.h>
0043 #include <linux/sysfs.h>
0044 #include <linux/module.h>
0045 #include <linux/io.h>
0046 #include <linux/atomic.h>
0047 #include <linux/cpu.h>
0048 
0049 #include <asm/fncpy.h>
0050 #include <asm/system_misc.h>
0051 #include <asm/irq.h>
0052 #include <asm/mach/time.h>
0053 #include <asm/mach/irq.h>
0054 
0055 #include <linux/soc/ti/omap1-io.h>
0056 #include "tc.h"
0057 #include <linux/omap-dma.h>
0058 #include <clocksource/timer-ti-dm.h>
0059 
0060 #include "hardware.h"
0061 #include "mux.h"
0062 #include "irqs.h"
0063 #include "iomap.h"
0064 #include "clock.h"
0065 #include "pm.h"
0066 #include "soc.h"
0067 #include "sram.h"
0068 
0069 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
0070 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
0071 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
0072 static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
0073 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
0074 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
0075 
0076 static unsigned short enable_dyn_sleep;
0077 
0078 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
0079              char *buf)
0080 {
0081     return sprintf(buf, "%hu\n", enable_dyn_sleep);
0082 }
0083 
0084 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
0085               const char * buf, size_t n)
0086 {
0087     unsigned short value;
0088     if (sscanf(buf, "%hu", &value) != 1 ||
0089         (value != 0 && value != 1) ||
0090         (value != 0 && !IS_ENABLED(CONFIG_OMAP_32K_TIMER))) {
0091         pr_err("idle_sleep_store: Invalid value\n");
0092         return -EINVAL;
0093     }
0094     enable_dyn_sleep = value;
0095     return n;
0096 }
0097 
0098 static struct kobj_attribute sleep_while_idle_attr =
0099     __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
0100 
0101 
0102 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
0103 
0104 /*
0105  * Let's power down on idle, but only if we are really
0106  * idle, because once we start down the path of
0107  * going idle we continue to do idle even if we get
0108  * a clock tick interrupt . .
0109  */
0110 void omap1_pm_idle(void)
0111 {
0112     extern __u32 arm_idlect1_mask;
0113     __u32 use_idlect1 = arm_idlect1_mask;
0114 
0115     local_fiq_disable();
0116 
0117 #if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
0118     use_idlect1 = use_idlect1 & ~(1 << 9);
0119 #endif
0120 
0121 #ifdef CONFIG_OMAP_DM_TIMER
0122     use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
0123 #endif
0124 
0125     if (omap_dma_running())
0126         use_idlect1 &= ~(1 << 6);
0127 
0128     /*
0129      * We should be able to remove the do_sleep variable and multiple
0130      * tests above as soon as drivers, timer and DMA code have been fixed.
0131      * Even the sleep block count should become obsolete.
0132      */
0133     if ((use_idlect1 != ~0) || !enable_dyn_sleep) {
0134 
0135         __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
0136         if (cpu_is_omap15xx())
0137             use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
0138         else
0139             use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
0140         omap_writel(use_idlect1, ARM_IDLECT1);
0141         __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
0142         omap_writel(saved_idlect1, ARM_IDLECT1);
0143 
0144         local_fiq_enable();
0145         return;
0146     }
0147     omap_sram_suspend(omap_readl(ARM_IDLECT1),
0148               omap_readl(ARM_IDLECT2));
0149 
0150     local_fiq_enable();
0151 }
0152 
0153 /*
0154  * Configuration of the wakeup event is board specific. For the
0155  * moment we put it into this helper function. Later it may move
0156  * to board specific files.
0157  */
0158 static void omap_pm_wakeup_setup(void)
0159 {
0160     u32 level1_wake = 0;
0161     u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
0162 
0163     /*
0164      * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
0165      * and the L2 wakeup interrupts: keypad and UART2. Note that the
0166      * drivers must still separately call omap_set_gpio_wakeup() to
0167      * wake up to a GPIO interrupt.
0168      */
0169     if (cpu_is_omap7xx())
0170         level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
0171             OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
0172     else if (cpu_is_omap15xx())
0173         level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
0174             OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
0175     else if (cpu_is_omap16xx())
0176         level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
0177             OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
0178 
0179     omap_writel(~level1_wake, OMAP_IH1_MIR);
0180 
0181     if (cpu_is_omap7xx()) {
0182         omap_writel(~level2_wake, OMAP_IH2_0_MIR);
0183         omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
0184                 OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
0185                 OMAP_IH2_1_MIR);
0186     } else if (cpu_is_omap15xx()) {
0187         level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
0188         omap_writel(~level2_wake,  OMAP_IH2_MIR);
0189     } else if (cpu_is_omap16xx()) {
0190         level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
0191         omap_writel(~level2_wake, OMAP_IH2_0_MIR);
0192 
0193         /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
0194         omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
0195                 OMAP_IH2_1_MIR);
0196         omap_writel(~0x0, OMAP_IH2_2_MIR);
0197         omap_writel(~0x0, OMAP_IH2_3_MIR);
0198     }
0199 
0200     /*  New IRQ agreement, recalculate in cascade order */
0201     omap_writel(1, OMAP_IH2_CONTROL);
0202     omap_writel(1, OMAP_IH1_CONTROL);
0203 }
0204 
0205 #define EN_DSPCK    13  /* ARM_CKCTL */
0206 #define EN_APICK    6   /* ARM_IDLECT2 */
0207 #define DSP_EN      1   /* ARM_RSTCT1 */
0208 
0209 void omap1_pm_suspend(void)
0210 {
0211     unsigned long arg0 = 0, arg1 = 0;
0212 
0213     printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n",
0214         omap_rev());
0215 
0216     omap_serial_wake_trigger(1);
0217 
0218     if (!cpu_is_omap15xx())
0219         omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
0220 
0221     /*
0222      * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
0223      */
0224 
0225     local_irq_disable();
0226     local_fiq_disable();
0227 
0228     /*
0229      * Step 2: save registers
0230      *
0231      * The omap is a strange/beautiful device. The caches, memory
0232      * and register state are preserved across power saves.
0233      * We have to save and restore very little register state to
0234      * idle the omap.
0235          *
0236      * Save interrupt, MPUI, ARM and UPLD control registers.
0237      */
0238 
0239     if (cpu_is_omap7xx()) {
0240         MPUI7XX_SAVE(OMAP_IH1_MIR);
0241         MPUI7XX_SAVE(OMAP_IH2_0_MIR);
0242         MPUI7XX_SAVE(OMAP_IH2_1_MIR);
0243         MPUI7XX_SAVE(MPUI_CTRL);
0244         MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
0245         MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
0246         MPUI7XX_SAVE(EMIFS_CONFIG);
0247         MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
0248 
0249     } else if (cpu_is_omap15xx()) {
0250         MPUI1510_SAVE(OMAP_IH1_MIR);
0251         MPUI1510_SAVE(OMAP_IH2_MIR);
0252         MPUI1510_SAVE(MPUI_CTRL);
0253         MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
0254         MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
0255         MPUI1510_SAVE(EMIFS_CONFIG);
0256         MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
0257     } else if (cpu_is_omap16xx()) {
0258         MPUI1610_SAVE(OMAP_IH1_MIR);
0259         MPUI1610_SAVE(OMAP_IH2_0_MIR);
0260         MPUI1610_SAVE(OMAP_IH2_1_MIR);
0261         MPUI1610_SAVE(OMAP_IH2_2_MIR);
0262         MPUI1610_SAVE(OMAP_IH2_3_MIR);
0263         MPUI1610_SAVE(MPUI_CTRL);
0264         MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
0265         MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
0266         MPUI1610_SAVE(EMIFS_CONFIG);
0267         MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
0268     }
0269 
0270     ARM_SAVE(ARM_CKCTL);
0271     ARM_SAVE(ARM_IDLECT1);
0272     ARM_SAVE(ARM_IDLECT2);
0273     if (!(cpu_is_omap15xx()))
0274         ARM_SAVE(ARM_IDLECT3);
0275     ARM_SAVE(ARM_EWUPCT);
0276     ARM_SAVE(ARM_RSTCT1);
0277     ARM_SAVE(ARM_RSTCT2);
0278     ARM_SAVE(ARM_SYSST);
0279     ULPD_SAVE(ULPD_CLOCK_CTRL);
0280     ULPD_SAVE(ULPD_STATUS_REQ);
0281 
0282     /* (Step 3 removed - we now allow deep sleep by default) */
0283 
0284     /*
0285      * Step 4: OMAP DSP Shutdown
0286      */
0287 
0288     /* stop DSP */
0289     omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
0290 
0291         /* shut down dsp_ck */
0292     if (!cpu_is_omap7xx())
0293         omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
0294 
0295     /* temporarily enabling api_ck to access DSP registers */
0296     omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
0297 
0298     /* save DSP registers */
0299     DSP_SAVE(DSP_IDLECT2);
0300 
0301     /* Stop all DSP domain clocks */
0302     __raw_writew(0, DSP_IDLECT2);
0303 
0304     /*
0305      * Step 5: Wakeup Event Setup
0306      */
0307 
0308     omap_pm_wakeup_setup();
0309 
0310     /*
0311      * Step 6: ARM and Traffic controller shutdown
0312      */
0313 
0314     /* disable ARM watchdog */
0315     omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
0316     omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
0317 
0318     /*
0319      * Step 6b: ARM and Traffic controller shutdown
0320      *
0321      * Step 6 continues here. Prepare jump to power management
0322      * assembly code in internal SRAM.
0323      *
0324      * Since the omap_cpu_suspend routine has been copied to
0325      * SRAM, we'll do an indirect procedure call to it and pass the
0326      * contents of arm_idlect1 and arm_idlect2 so it can restore
0327      * them when it wakes up and it will return.
0328      */
0329 
0330     arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
0331     arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
0332 
0333     /*
0334      * Step 6c: ARM and Traffic controller shutdown
0335      *
0336      * Jump to assembly code. The processor will stay there
0337      * until wake up.
0338      */
0339     omap_sram_suspend(arg0, arg1);
0340 
0341     /*
0342      * If we are here, processor is woken up!
0343      */
0344 
0345     /*
0346      * Restore DSP clocks
0347      */
0348 
0349     /* again temporarily enabling api_ck to access DSP registers */
0350     omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
0351 
0352     /* Restore DSP domain clocks */
0353     DSP_RESTORE(DSP_IDLECT2);
0354 
0355     /*
0356      * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
0357      */
0358 
0359     if (!(cpu_is_omap15xx()))
0360         ARM_RESTORE(ARM_IDLECT3);
0361     ARM_RESTORE(ARM_CKCTL);
0362     ARM_RESTORE(ARM_EWUPCT);
0363     ARM_RESTORE(ARM_RSTCT1);
0364     ARM_RESTORE(ARM_RSTCT2);
0365     ARM_RESTORE(ARM_SYSST);
0366     ULPD_RESTORE(ULPD_CLOCK_CTRL);
0367     ULPD_RESTORE(ULPD_STATUS_REQ);
0368 
0369     if (cpu_is_omap7xx()) {
0370         MPUI7XX_RESTORE(EMIFS_CONFIG);
0371         MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
0372         MPUI7XX_RESTORE(OMAP_IH1_MIR);
0373         MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
0374         MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
0375     } else if (cpu_is_omap15xx()) {
0376         MPUI1510_RESTORE(MPUI_CTRL);
0377         MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
0378         MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
0379         MPUI1510_RESTORE(EMIFS_CONFIG);
0380         MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
0381         MPUI1510_RESTORE(OMAP_IH1_MIR);
0382         MPUI1510_RESTORE(OMAP_IH2_MIR);
0383     } else if (cpu_is_omap16xx()) {
0384         MPUI1610_RESTORE(MPUI_CTRL);
0385         MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
0386         MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
0387         MPUI1610_RESTORE(EMIFS_CONFIG);
0388         MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
0389 
0390         MPUI1610_RESTORE(OMAP_IH1_MIR);
0391         MPUI1610_RESTORE(OMAP_IH2_0_MIR);
0392         MPUI1610_RESTORE(OMAP_IH2_1_MIR);
0393         MPUI1610_RESTORE(OMAP_IH2_2_MIR);
0394         MPUI1610_RESTORE(OMAP_IH2_3_MIR);
0395     }
0396 
0397     if (!cpu_is_omap15xx())
0398         omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
0399 
0400     /*
0401      * Re-enable interrupts
0402      */
0403 
0404     local_irq_enable();
0405     local_fiq_enable();
0406 
0407     omap_serial_wake_trigger(0);
0408 
0409     printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
0410         omap_rev());
0411 }
0412 
0413 #ifdef CONFIG_DEBUG_FS
0414 /*
0415  * Read system PM registers for debugging
0416  */
0417 static int omap_pm_debug_show(struct seq_file *m, void *v)
0418 {
0419     ARM_SAVE(ARM_CKCTL);
0420     ARM_SAVE(ARM_IDLECT1);
0421     ARM_SAVE(ARM_IDLECT2);
0422     if (!(cpu_is_omap15xx()))
0423         ARM_SAVE(ARM_IDLECT3);
0424     ARM_SAVE(ARM_EWUPCT);
0425     ARM_SAVE(ARM_RSTCT1);
0426     ARM_SAVE(ARM_RSTCT2);
0427     ARM_SAVE(ARM_SYSST);
0428 
0429     ULPD_SAVE(ULPD_IT_STATUS);
0430     ULPD_SAVE(ULPD_CLOCK_CTRL);
0431     ULPD_SAVE(ULPD_SOFT_REQ);
0432     ULPD_SAVE(ULPD_STATUS_REQ);
0433     ULPD_SAVE(ULPD_DPLL_CTRL);
0434     ULPD_SAVE(ULPD_POWER_CTRL);
0435 
0436     if (cpu_is_omap7xx()) {
0437         MPUI7XX_SAVE(MPUI_CTRL);
0438         MPUI7XX_SAVE(MPUI_DSP_STATUS);
0439         MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
0440         MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
0441         MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
0442         MPUI7XX_SAVE(EMIFS_CONFIG);
0443     } else if (cpu_is_omap15xx()) {
0444         MPUI1510_SAVE(MPUI_CTRL);
0445         MPUI1510_SAVE(MPUI_DSP_STATUS);
0446         MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
0447         MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
0448         MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
0449         MPUI1510_SAVE(EMIFS_CONFIG);
0450     } else if (cpu_is_omap16xx()) {
0451         MPUI1610_SAVE(MPUI_CTRL);
0452         MPUI1610_SAVE(MPUI_DSP_STATUS);
0453         MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
0454         MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
0455         MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
0456         MPUI1610_SAVE(EMIFS_CONFIG);
0457     }
0458 
0459     seq_printf(m,
0460            "ARM_CKCTL_REG:            0x%-8x     \n"
0461            "ARM_IDLECT1_REG:          0x%-8x     \n"
0462            "ARM_IDLECT2_REG:          0x%-8x     \n"
0463            "ARM_IDLECT3_REG:          0x%-8x     \n"
0464            "ARM_EWUPCT_REG:           0x%-8x     \n"
0465            "ARM_RSTCT1_REG:           0x%-8x     \n"
0466            "ARM_RSTCT2_REG:           0x%-8x     \n"
0467            "ARM_SYSST_REG:            0x%-8x     \n"
0468            "ULPD_IT_STATUS_REG:       0x%-4x     \n"
0469            "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
0470            "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
0471            "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
0472            "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
0473            "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
0474            ARM_SHOW(ARM_CKCTL),
0475            ARM_SHOW(ARM_IDLECT1),
0476            ARM_SHOW(ARM_IDLECT2),
0477            ARM_SHOW(ARM_IDLECT3),
0478            ARM_SHOW(ARM_EWUPCT),
0479            ARM_SHOW(ARM_RSTCT1),
0480            ARM_SHOW(ARM_RSTCT2),
0481            ARM_SHOW(ARM_SYSST),
0482            ULPD_SHOW(ULPD_IT_STATUS),
0483            ULPD_SHOW(ULPD_CLOCK_CTRL),
0484            ULPD_SHOW(ULPD_SOFT_REQ),
0485            ULPD_SHOW(ULPD_DPLL_CTRL),
0486            ULPD_SHOW(ULPD_STATUS_REQ),
0487            ULPD_SHOW(ULPD_POWER_CTRL));
0488 
0489     if (cpu_is_omap7xx()) {
0490         seq_printf(m,
0491                "MPUI7XX_CTRL_REG         0x%-8x \n"
0492                "MPUI7XX_DSP_STATUS_REG:      0x%-8x \n"
0493                "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
0494                "MPUI7XX_DSP_API_CONFIG_REG:  0x%-8x \n"
0495                "MPUI7XX_SDRAM_CONFIG_REG:    0x%-8x \n"
0496                "MPUI7XX_EMIFS_CONFIG_REG:    0x%-8x \n",
0497                MPUI7XX_SHOW(MPUI_CTRL),
0498                MPUI7XX_SHOW(MPUI_DSP_STATUS),
0499                MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
0500                MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
0501                MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
0502                MPUI7XX_SHOW(EMIFS_CONFIG));
0503     } else if (cpu_is_omap15xx()) {
0504         seq_printf(m,
0505                "MPUI1510_CTRL_REG             0x%-8x \n"
0506                "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
0507                "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
0508                "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
0509                "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
0510                "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
0511                MPUI1510_SHOW(MPUI_CTRL),
0512                MPUI1510_SHOW(MPUI_DSP_STATUS),
0513                MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
0514                MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
0515                MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
0516                MPUI1510_SHOW(EMIFS_CONFIG));
0517     } else if (cpu_is_omap16xx()) {
0518         seq_printf(m,
0519                "MPUI1610_CTRL_REG             0x%-8x \n"
0520                "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
0521                "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
0522                "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
0523                "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
0524                "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
0525                MPUI1610_SHOW(MPUI_CTRL),
0526                MPUI1610_SHOW(MPUI_DSP_STATUS),
0527                MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
0528                MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
0529                MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
0530                MPUI1610_SHOW(EMIFS_CONFIG));
0531     }
0532 
0533     return 0;
0534 }
0535 
0536 DEFINE_SHOW_ATTRIBUTE(omap_pm_debug);
0537 
0538 static void omap_pm_init_debugfs(void)
0539 {
0540     struct dentry *d;
0541 
0542     d = debugfs_create_dir("pm_debug", NULL);
0543     debugfs_create_file("omap_pm", S_IWUSR | S_IRUGO, d, NULL,
0544                 &omap_pm_debug_fops);
0545 }
0546 
0547 #endif /* CONFIG_DEBUG_FS */
0548 
0549 /*
0550  *  omap_pm_prepare - Do preliminary suspend work.
0551  *
0552  */
0553 static int omap_pm_prepare(void)
0554 {
0555     /* We cannot sleep in idle until we have resumed */
0556     cpu_idle_poll_ctrl(true);
0557     return 0;
0558 }
0559 
0560 
0561 /*
0562  *  omap_pm_enter - Actually enter a sleep state.
0563  *  @state:     State we're entering.
0564  *
0565  */
0566 
0567 static int omap_pm_enter(suspend_state_t state)
0568 {
0569     switch (state)
0570     {
0571     case PM_SUSPEND_MEM:
0572         omap1_pm_suspend();
0573         break;
0574     default:
0575         return -EINVAL;
0576     }
0577 
0578     return 0;
0579 }
0580 
0581 
0582 /**
0583  *  omap_pm_finish - Finish up suspend sequence.
0584  *
0585  *  This is called after we wake back up (or if entering the sleep state
0586  *  failed).
0587  */
0588 
0589 static void omap_pm_finish(void)
0590 {
0591     cpu_idle_poll_ctrl(false);
0592 }
0593 
0594 
0595 static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
0596 {
0597     return IRQ_HANDLED;
0598 }
0599 
0600 
0601 
0602 static const struct platform_suspend_ops omap_pm_ops = {
0603     .prepare    = omap_pm_prepare,
0604     .enter      = omap_pm_enter,
0605     .finish     = omap_pm_finish,
0606     .valid      = suspend_valid_only_mem,
0607 };
0608 
0609 static int __init omap_pm_init(void)
0610 {
0611     int error = 0;
0612     int irq;
0613 
0614     if (!cpu_class_is_omap1())
0615         return -ENODEV;
0616 
0617     pr_info("Power Management for TI OMAP.\n");
0618 
0619     if (!IS_ENABLED(CONFIG_OMAP_32K_TIMER))
0620         pr_info("OMAP1 PM: sleep states in idle disabled due to no 32KiHz timer\n");
0621 
0622     if (!IS_ENABLED(CONFIG_OMAP_DM_TIMER))
0623         pr_info("OMAP1 PM: sleep states in idle disabled due to no DMTIMER support\n");
0624 
0625     if (IS_ENABLED(CONFIG_OMAP_32K_TIMER) &&
0626         IS_ENABLED(CONFIG_OMAP_DM_TIMER)) {
0627         /* OMAP16xx only */
0628         pr_info("OMAP1 PM: sleep states in idle enabled\n");
0629         enable_dyn_sleep = 1;
0630     }
0631 
0632     /*
0633      * We copy the assembler sleep/wakeup routines to SRAM.
0634      * These routines need to be in SRAM as that's the only
0635      * memory the MPU can see when it wakes up.
0636      */
0637     if (cpu_is_omap7xx()) {
0638         omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
0639                            omap7xx_cpu_suspend_sz);
0640     } else if (cpu_is_omap15xx()) {
0641         omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
0642                            omap1510_cpu_suspend_sz);
0643     } else if (cpu_is_omap16xx()) {
0644         omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
0645                            omap1610_cpu_suspend_sz);
0646     }
0647 
0648     if (omap_sram_suspend == NULL) {
0649         printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
0650         return -ENODEV;
0651     }
0652 
0653     arm_pm_idle = omap1_pm_idle;
0654 
0655     if (cpu_is_omap7xx())
0656         irq = INT_7XX_WAKE_UP_REQ;
0657     else if (cpu_is_omap16xx())
0658         irq = INT_1610_WAKE_UP_REQ;
0659     else
0660         irq = -1;
0661 
0662     if (irq >= 0) {
0663         if (request_irq(irq, omap_wakeup_interrupt, 0, "peripheral wakeup", NULL))
0664             pr_err("Failed to request irq %d (peripheral wakeup)\n", irq);
0665     }
0666 
0667     /* Program new power ramp-up time
0668      * (0 for most boards since we don't lower voltage when in deep sleep)
0669      */
0670     omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
0671 
0672     /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
0673     omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
0674 
0675     /* Configure IDLECT3 */
0676     if (cpu_is_omap7xx())
0677         omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
0678     else if (cpu_is_omap16xx())
0679         omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
0680 
0681     suspend_set_ops(&omap_pm_ops);
0682 
0683 #ifdef CONFIG_DEBUG_FS
0684     omap_pm_init_debugfs();
0685 #endif
0686 
0687     error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
0688     if (error)
0689         printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
0690 
0691     if (cpu_is_omap16xx()) {
0692         /* configure LOW_PWR pin */
0693         omap_cfg_reg(T20_1610_LOW_PWR);
0694     }
0695 
0696     return error;
0697 }
0698 __initcall(omap_pm_init);
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