arm/mach-omap1/omap16xx.h

0001 /*
0002  * Hardware definitions for TI OMAP1610/5912/1710 processors.
0003  *
0004  * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
0005  *
0006  * This program is free software; you can redistribute it and/or modify it
0007  * under the terms of the GNU General Public License as published by the
0008  * Free Software Foundation; either version 2 of the License, or (at your
0009  * option) any later version.
0010  *
0011  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
0012  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
0013  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
0014  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
0015  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0016  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
0017  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0018  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0019  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0020  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0021  *
0022  * You should have received a copy of the  GNU General Public License along
0023  * with this program; if not, write  to the Free Software Foundation, Inc.,
0024  * 675 Mass Ave, Cambridge, MA 02139, USA.
0025  */
0026
0027 #ifndef __ASM_ARCH_OMAP16XX_H
0028 #define __ASM_ARCH_OMAP16XX_H
0029
0030 /*
0031  * ----------------------------------------------------------------------------
0032  * Base addresses
0033  * ----------------------------------------------------------------------------
0034  */
0035
0036 /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
0037
0038 #define OMAP16XX_DSP_BASE   0xE0000000
0039 #define OMAP16XX_DSP_SIZE   0x28000
0040 #define OMAP16XX_DSP_START  0xE0000000
0041
0042 #define OMAP16XX_DSPREG_BASE    0xE1000000
0043 #define OMAP16XX_DSPREG_SIZE    SZ_128K
0044 #define OMAP16XX_DSPREG_START   0xE1000000
0045
0046 #define OMAP16XX_SEC_BASE   0xFFFE4000
0047 #define OMAP16XX_SEC_DES    (OMAP16XX_SEC_BASE + 0x0000)
0048 #define OMAP16XX_SEC_SHA1MD5    (OMAP16XX_SEC_BASE + 0x0800)
0049 #define OMAP16XX_SEC_RNG    (OMAP16XX_SEC_BASE + 0x1000)
0050
0051 /*
0052  * ---------------------------------------------------------------------------
0053  * Interrupts
0054  * ---------------------------------------------------------------------------
0055  */
0056 #define OMAP_IH2_0_BASE     (0xfffe0000)
0057 #define OMAP_IH2_1_BASE     (0xfffe0100)
0058 #define OMAP_IH2_2_BASE     (0xfffe0200)
0059 #define OMAP_IH2_3_BASE     (0xfffe0300)
0060
0061 #define OMAP_IH2_0_ITR      (OMAP_IH2_0_BASE + 0x00)
0062 #define OMAP_IH2_0_MIR      (OMAP_IH2_0_BASE + 0x04)
0063 #define OMAP_IH2_0_SIR_IRQ  (OMAP_IH2_0_BASE + 0x10)
0064 #define OMAP_IH2_0_SIR_FIQ  (OMAP_IH2_0_BASE + 0x14)
0065 #define OMAP_IH2_0_CONTROL  (OMAP_IH2_0_BASE + 0x18)
0066 #define OMAP_IH2_0_ILR0     (OMAP_IH2_0_BASE + 0x1c)
0067 #define OMAP_IH2_0_ISR      (OMAP_IH2_0_BASE + 0x9c)
0068
0069 #define OMAP_IH2_1_ITR      (OMAP_IH2_1_BASE + 0x00)
0070 #define OMAP_IH2_1_MIR      (OMAP_IH2_1_BASE + 0x04)
0071 #define OMAP_IH2_1_SIR_IRQ  (OMAP_IH2_1_BASE + 0x10)
0072 #define OMAP_IH2_1_SIR_FIQ  (OMAP_IH2_1_BASE + 0x14)
0073 #define OMAP_IH2_1_CONTROL  (OMAP_IH2_1_BASE + 0x18)
0074 #define OMAP_IH2_1_ILR1     (OMAP_IH2_1_BASE + 0x1c)
0075 #define OMAP_IH2_1_ISR      (OMAP_IH2_1_BASE + 0x9c)
0076
0077 #define OMAP_IH2_2_ITR      (OMAP_IH2_2_BASE + 0x00)
0078 #define OMAP_IH2_2_MIR      (OMAP_IH2_2_BASE + 0x04)
0079 #define OMAP_IH2_2_SIR_IRQ  (OMAP_IH2_2_BASE + 0x10)
0080 #define OMAP_IH2_2_SIR_FIQ  (OMAP_IH2_2_BASE + 0x14)
0081 #define OMAP_IH2_2_CONTROL  (OMAP_IH2_2_BASE + 0x18)
0082 #define OMAP_IH2_2_ILR2     (OMAP_IH2_2_BASE + 0x1c)
0083 #define OMAP_IH2_2_ISR      (OMAP_IH2_2_BASE + 0x9c)
0084
0085 #define OMAP_IH2_3_ITR      (OMAP_IH2_3_BASE + 0x00)
0086 #define OMAP_IH2_3_MIR      (OMAP_IH2_3_BASE + 0x04)
0087 #define OMAP_IH2_3_SIR_IRQ  (OMAP_IH2_3_BASE + 0x10)
0088 #define OMAP_IH2_3_SIR_FIQ  (OMAP_IH2_3_BASE + 0x14)
0089 #define OMAP_IH2_3_CONTROL  (OMAP_IH2_3_BASE + 0x18)
0090 #define OMAP_IH2_3_ILR3     (OMAP_IH2_3_BASE + 0x1c)
0091 #define OMAP_IH2_3_ISR      (OMAP_IH2_3_BASE + 0x9c)
0092
0093 /*
0094  * ----------------------------------------------------------------------------
0095  * Clocks
0096  * ----------------------------------------------------------------------------
0097  */
0098 #define OMAP16XX_ARM_IDLECT3    (CLKGEN_REG_BASE + 0x24)
0099
0100 /*
0101  * ----------------------------------------------------------------------------
0102  * Pin configuration registers
0103  * ----------------------------------------------------------------------------
0104  */
0105 #define OMAP16XX_CONF_VOLTAGE_VDDSHV6   (1 << 8)
0106 #define OMAP16XX_CONF_VOLTAGE_VDDSHV7   (1 << 9)
0107 #define OMAP16XX_CONF_VOLTAGE_VDDSHV8   (1 << 10)
0108 #define OMAP16XX_CONF_VOLTAGE_VDDSHV9   (1 << 11)
0109 #define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
0110
0111 /*
0112  * ----------------------------------------------------------------------------
0113  * System control registers
0114  * ----------------------------------------------------------------------------
0115  */
0116 #define OMAP1610_RESET_CONTROL  0xfffe1140
0117
0118 /*
0119  * ---------------------------------------------------------------------------
0120  * TIPB bus interface
0121  * ---------------------------------------------------------------------------
0122  */
0123 #define TIPB_SWITCH_BASE         (0xfffbc800)
0124 #define OMAP16XX_MMCSD2_SSW_MPU_CONF    (TIPB_SWITCH_BASE + 0x160)
0125
0126 /* UART3 Registers Mapping through MPU bus */
0127 #define UART3_RHR               (OMAP1_UART3_BASE + 0)
0128 #define UART3_THR               (OMAP1_UART3_BASE + 0)
0129 #define UART3_DLL               (OMAP1_UART3_BASE + 0)
0130 #define UART3_IER               (OMAP1_UART3_BASE + 4)
0131 #define UART3_DLH               (OMAP1_UART3_BASE + 4)
0132 #define UART3_IIR               (OMAP1_UART3_BASE + 8)
0133 #define UART3_FCR               (OMAP1_UART3_BASE + 8)
0134 #define UART3_EFR               (OMAP1_UART3_BASE + 8)
0135 #define UART3_LCR               (OMAP1_UART3_BASE + 0x0C)
0136 #define UART3_MCR               (OMAP1_UART3_BASE + 0x10)
0137 #define UART3_XON1_ADDR1        (OMAP1_UART3_BASE + 0x10)
0138 #define UART3_XON2_ADDR2        (OMAP1_UART3_BASE + 0x14)
0139 #define UART3_LSR               (OMAP1_UART3_BASE + 0x14)
0140 #define UART3_TCR               (OMAP1_UART3_BASE + 0x18)
0141 #define UART3_MSR               (OMAP1_UART3_BASE + 0x18)
0142 #define UART3_XOFF1             (OMAP1_UART3_BASE + 0x18)
0143 #define UART3_XOFF2             (OMAP1_UART3_BASE + 0x1C)
0144 #define UART3_SPR               (OMAP1_UART3_BASE + 0x1C)
0145 #define UART3_TLR               (OMAP1_UART3_BASE + 0x1C)
0146 #define UART3_MDR1              (OMAP1_UART3_BASE + 0x20)
0147 #define UART3_MDR2              (OMAP1_UART3_BASE + 0x24)
0148 #define UART3_SFLSR             (OMAP1_UART3_BASE + 0x28)
0149 #define UART3_TXFLL             (OMAP1_UART3_BASE + 0x28)
0150 #define UART3_RESUME            (OMAP1_UART3_BASE + 0x2C)
0151 #define UART3_TXFLH             (OMAP1_UART3_BASE + 0x2C)
0152 #define UART3_SFREGL            (OMAP1_UART3_BASE + 0x30)
0153 #define UART3_RXFLL             (OMAP1_UART3_BASE + 0x30)
0154 #define UART3_SFREGH            (OMAP1_UART3_BASE + 0x34)
0155 #define UART3_RXFLH             (OMAP1_UART3_BASE + 0x34)
0156 #define UART3_BLR               (OMAP1_UART3_BASE + 0x38)
0157 #define UART3_ACREG             (OMAP1_UART3_BASE + 0x3C)
0158 #define UART3_DIV16             (OMAP1_UART3_BASE + 0x3C)
0159 #define UART3_SCR               (OMAP1_UART3_BASE + 0x40)
0160 #define UART3_SSR               (OMAP1_UART3_BASE + 0x44)
0161 #define UART3_EBLR              (OMAP1_UART3_BASE + 0x48)
0162 #define UART3_OSC_12M_SEL       (OMAP1_UART3_BASE + 0x4C)
0163 #define UART3_MVR               (OMAP1_UART3_BASE + 0x50)
0164
0165 /*
0166  * ---------------------------------------------------------------------------
0167  * Watchdog timer
0168  * ---------------------------------------------------------------------------
0169  */
0170
0171 /* 32-bit Watchdog timer in OMAP 16XX */
0172 #define OMAP_16XX_WATCHDOG_BASE        (0xfffeb000)
0173 #define OMAP_16XX_WIDR         (OMAP_16XX_WATCHDOG_BASE + 0x00)
0174 #define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
0175 #define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
0176 #define OMAP_16XX_WCLR         (OMAP_16XX_WATCHDOG_BASE + 0x24)
0177 #define OMAP_16XX_WCRR         (OMAP_16XX_WATCHDOG_BASE + 0x28)
0178 #define OMAP_16XX_WLDR         (OMAP_16XX_WATCHDOG_BASE + 0x2c)
0179 #define OMAP_16XX_WTGR         (OMAP_16XX_WATCHDOG_BASE + 0x30)
0180 #define OMAP_16XX_WWPS         (OMAP_16XX_WATCHDOG_BASE + 0x34)
0181 #define OMAP_16XX_WSPR         (OMAP_16XX_WATCHDOG_BASE + 0x48)
0182
0183 #define WCLR_PRE_SHIFT         5
0184 #define WCLR_PTV_SHIFT         2
0185
0186 #define WWPS_W_PEND_WSPR       (1 << 4)
0187 #define WWPS_W_PEND_WTGR       (1 << 3)
0188 #define WWPS_W_PEND_WLDR       (1 << 2)
0189 #define WWPS_W_PEND_WCRR       (1 << 1)
0190 #define WWPS_W_PEND_WCLR       (1 << 0)
0191
0192 #define WSPR_ENABLE_0          (0x0000bbbb)
0193 #define WSPR_ENABLE_1          (0x00004444)
0194 #define WSPR_DISABLE_0         (0x0000aaaa)
0195 #define WSPR_DISABLE_1         (0x00005555)
0196
0197 #define OMAP16XX_DSP_MMU_BASE   (0xfffed200)
0198 #define OMAP16XX_MAILBOX_BASE   (0xfffcf000)
0199
0200 #endif /*  __ASM_ARCH_OMAP16XX_H */
0201