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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * linux/arch/arm/mach-omap1/mux.c
0004  *
0005  * OMAP1 pin multiplexing configurations
0006  *
0007  * Copyright (C) 2003 - 2008 Nokia Corporation
0008  *
0009  * Written by Tony Lindgren
0010  */
0011 #include <linux/module.h>
0012 #include <linux/init.h>
0013 #include <linux/io.h>
0014 #include <linux/spinlock.h>
0015 #include <linux/soc/ti/omap1-io.h>
0016 
0017 #include "hardware.h"
0018 #include "mux.h"
0019 
0020 #ifdef CONFIG_OMAP_MUX
0021 
0022 static struct omap_mux_cfg arch_mux_cfg;
0023 
0024 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
0025 static struct pin_config omap7xx_pins[] = {
0026 MUX_CFG_7XX("E2_7XX_KBR0",        12,   21,    0,   20,   1, 0)
0027 MUX_CFG_7XX("J7_7XX_KBR1",        12,   25,    0,   24,   1, 0)
0028 MUX_CFG_7XX("E1_7XX_KBR2",        12,   29,    0,   28,   1, 0)
0029 MUX_CFG_7XX("F3_7XX_KBR3",        13,    1,    0,    0,   1, 0)
0030 MUX_CFG_7XX("D2_7XX_KBR4",        13,    5,    0,    4,   1, 0)
0031 MUX_CFG_7XX("C2_7XX_KBC0",        13,    9,    0,    8,   1, 0)
0032 MUX_CFG_7XX("D3_7XX_KBC1",        13,   13,    0,   12,   1, 0)
0033 MUX_CFG_7XX("E4_7XX_KBC2",        13,   17,    0,   16,   1, 0)
0034 MUX_CFG_7XX("F4_7XX_KBC3",        13,   21,    0,   20,   1, 0)
0035 MUX_CFG_7XX("E3_7XX_KBC4",        13,   25,    0,   24,   1, 0)
0036 
0037 MUX_CFG_7XX("AA17_7XX_USB_DM",     2,   21,    0,   20,   0, 0)
0038 MUX_CFG_7XX("W16_7XX_USB_PU_EN",   2,   25,    0,   24,   0, 0)
0039 MUX_CFG_7XX("W17_7XX_USB_VBUSI",   2,   29,    6,   28,   1, 0)
0040 MUX_CFG_7XX("W18_7XX_USB_DMCK_OUT",3,    3,    1,    2,   0, 0)
0041 MUX_CFG_7XX("W19_7XX_USB_DCRST",   3,    7,    1,    6,   0, 0)
0042 
0043 /* MMC Pins */
0044 MUX_CFG_7XX("MMC_7XX_CMD",         2,    9,    0,    8,   1, 0)
0045 MUX_CFG_7XX("MMC_7XX_CLK",         2,   13,    0,   12,   1, 0)
0046 MUX_CFG_7XX("MMC_7XX_DAT0",        2,   17,    0,   16,   1, 0)
0047 
0048 /* I2C interface */
0049 MUX_CFG_7XX("I2C_7XX_SCL",         5,    1,    0,    0,   1, 0)
0050 MUX_CFG_7XX("I2C_7XX_SDA",         5,    5,    0,    0,   1, 0)
0051 
0052 /* SPI pins */
0053 MUX_CFG_7XX("SPI_7XX_1",           6,    5,    4,    4,   1, 0)
0054 MUX_CFG_7XX("SPI_7XX_2",           6,    9,    4,    8,   1, 0)
0055 MUX_CFG_7XX("SPI_7XX_3",           6,   13,    4,   12,   1, 0)
0056 MUX_CFG_7XX("SPI_7XX_4",           6,   17,    4,   16,   1, 0)
0057 MUX_CFG_7XX("SPI_7XX_5",           8,   25,    0,   24,   0, 0)
0058 MUX_CFG_7XX("SPI_7XX_6",           9,    5,    0,    4,   0, 0)
0059 
0060 /* UART pins */
0061 MUX_CFG_7XX("UART_7XX_1",          3,   21,    0,   20,   0, 0)
0062 MUX_CFG_7XX("UART_7XX_2",          8,    1,    6,    0,   0, 0)
0063 };
0064 #define OMAP7XX_PINS_SZ     ARRAY_SIZE(omap7xx_pins)
0065 #else
0066 #define omap7xx_pins        NULL
0067 #define OMAP7XX_PINS_SZ     0
0068 #endif  /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
0069 
0070 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
0071 static struct pin_config omap1xxx_pins[] = {
0072 /*
0073  *   description        mux  mode   mux  pull pull  pull  pu_pd  pu  dbg
0074  *              reg  offset mode reg  bit   ena   reg
0075  */
0076 MUX_CFG("UART1_TX",      9,   21,    1,   2,   3,   0,   NA,     0,  0)
0077 MUX_CFG("UART1_RTS",         9,   12,    1,   2,   0,   0,   NA,     0,  0)
0078 
0079 /* UART2 (COM_UART_GATING), conflicts with USB2 */
0080 MUX_CFG("UART2_TX",      C,   27,    1,   3,   3,   0,   NA,     0,  0)
0081 MUX_CFG("UART2_RX",      C,   18,    0,   3,   1,   1,   NA,     0,  0)
0082 MUX_CFG("UART2_CTS",         C,   21,    0,   3,   1,   1,   NA,     0,  0)
0083 MUX_CFG("UART2_RTS",         C,   24,    1,   3,   2,   0,   NA,     0,  0)
0084 
0085 /* UART3 (GIGA_UART_GATING) */
0086 MUX_CFG("UART3_TX",      6,    0,    1,   0,  30,   0,   NA,     0,  0)
0087 MUX_CFG("UART3_RX",      6,    3,    0,   0,  31,   1,   NA,     0,  0)
0088 MUX_CFG("UART3_CTS",         5,   12,    2,   0,  24,   0,   NA,     0,  0)
0089 MUX_CFG("UART3_RTS",         5,   15,    2,   0,  25,   0,   NA,     0,  0)
0090 MUX_CFG("UART3_CLKREQ",      9,   27,    0,   2,   5,   0,   NA,     0,  0)
0091 MUX_CFG("UART3_BCLK",        A,    0,    0,   2,   6,   0,   NA,     0,  0)
0092 MUX_CFG("Y15_1610_UART3_RTS",    A,    0,    1,   2,   6,   0,   NA,     0,  0)
0093 
0094 /* PWT & PWL, conflicts with UART3 */
0095 MUX_CFG("PWT",           6,    0,    2,   0,  30,   0,   NA,     0,  0)
0096 MUX_CFG("PWL",           6,    3,    1,   0,  31,   1,   NA,     0,  0)
0097 
0098 /* USB internal master generic */
0099 MUX_CFG("R18_USB_VBUS",      7,    9,    2,   1,  11,   0,   NA,     0,  1)
0100 MUX_CFG("R18_1510_USB_GPIO0",    7,    9,    0,   1,  11,   1,   NA,     0,  1)
0101 /* works around erratum:  W4_USB_PUEN and W4_USB_PUDIS are switched! */
0102 MUX_CFG("W4_USB_PUEN",       D,    3,    3,   3,   5,   1,   NA,     0,  1)
0103 MUX_CFG("W4_USB_CLKO",       D,    3,    1,   3,   5,   0,   NA,     0,  1)
0104 MUX_CFG("W4_USB_HIGHZ",      D,    3,    4,   3,   5,   0,    3,     0,  1)
0105 MUX_CFG("W4_GPIO58",         D,    3,    7,   3,   5,   0,    3,     0,  1)
0106 
0107 /* USB1 master */
0108 MUX_CFG("USB1_SUSP",         8,   27,    2,   1,  27,   0,   NA,     0,  1)
0109 MUX_CFG("USB1_SE0",      9,    0,    2,   1,  28,   0,   NA,     0,  1)
0110 MUX_CFG("W13_1610_USB1_SE0",     9,    0,    4,   1,  28,   0,   NA,     0,  1)
0111 MUX_CFG("USB1_TXEN",         9,    3,    2,   1,  29,   0,   NA,     0,  1)
0112 MUX_CFG("USB1_TXD",      9,   24,    1,   2,   4,   0,   NA,     0,  1)
0113 MUX_CFG("USB1_VP",       A,    3,    1,   2,   7,   0,   NA,     0,  1)
0114 MUX_CFG("USB1_VM",       A,    6,    1,   2,   8,   0,   NA,     0,  1)
0115 MUX_CFG("USB1_RCV",      A,    9,    1,   2,   9,   0,   NA,     0,  1)
0116 MUX_CFG("USB1_SPEED",        A,   12,    2,   2,  10,   0,   NA,     0,  1)
0117 MUX_CFG("R13_1610_USB1_SPEED",   A,   12,    5,   2,  10,   0,   NA,     0,  1)
0118 MUX_CFG("R13_1710_USB1_SEO",     A,   12,    5,   2,  10,   0,   NA,     0,  1)
0119 
0120 /* USB2 master */
0121 MUX_CFG("USB2_SUSP",         B,    3,    1,   2,  17,   0,   NA,     0,  1)
0122 MUX_CFG("USB2_VP",       B,    6,    1,   2,  18,   0,   NA,     0,  1)
0123 MUX_CFG("USB2_TXEN",         B,    9,    1,   2,  19,   0,   NA,     0,  1)
0124 MUX_CFG("USB2_VM",       C,   18,    1,   3,   0,   0,   NA,     0,  1)
0125 MUX_CFG("USB2_RCV",      C,   21,    1,   3,   1,   0,   NA,     0,  1)
0126 MUX_CFG("USB2_SE0",      C,   24,    2,   3,   2,   0,   NA,     0,  1)
0127 MUX_CFG("USB2_TXD",      C,   27,    2,   3,   3,   0,   NA,     0,  1)
0128 
0129 /* OMAP-1510 GPIO */
0130 MUX_CFG("R18_1510_GPIO0",    7,    9,    0,   1,  11,   1,    0,     0,  1)
0131 MUX_CFG("R19_1510_GPIO1",    7,    6,    0,   1,  10,   1,    0,     0,  1)
0132 MUX_CFG("M14_1510_GPIO2",    7,    3,    0,   1,   9,   1,    0,     0,  1)
0133 
0134 /* OMAP1610 GPIO */
0135 MUX_CFG("P18_1610_GPIO3",    7,    0,    0,   1,   8,   0,   NA,     0,  1)
0136 MUX_CFG("Y15_1610_GPIO17",   A,    0,    7,   2,   6,   0,   NA,     0,  1)
0137 
0138 /* OMAP-1710 GPIO */
0139 MUX_CFG("R18_1710_GPIO0",        7,    9,    0,   1,  11,   1,    1,     1,  1)
0140 MUX_CFG("V2_1710_GPIO10",        F,   27,    1,   4,   3,   1,    4,     1,  1)
0141 MUX_CFG("N21_1710_GPIO14",       6,    9,    0,   1,   1,   1,    1,     1,  1)
0142 MUX_CFG("W15_1710_GPIO40",       9,   27,    7,   2,   5,   1,    2,     1,  1)
0143 
0144 /* MPUIO */
0145 MUX_CFG("MPUIO2",        7,   18,    0,   1,  14,   1,   NA,     0,  1)
0146 MUX_CFG("N15_1610_MPUIO2",   7,   18,    0,   1,  14,   1,    1,     0,  1)
0147 MUX_CFG("MPUIO4",        7,   15,    0,   1,  13,   1,   NA,     0,  1)
0148 MUX_CFG("MPUIO5",        7,   12,    0,   1,  12,   1,   NA,     0,  1)
0149 
0150 MUX_CFG("T20_1610_MPUIO5",   7,   12,    0,   1,  12,   0,    3,     0,  1)
0151 MUX_CFG("W11_1610_MPUIO6",  10,   15,    2,   3,   8,   0,    3,     0,  1)
0152 MUX_CFG("V10_1610_MPUIO7",   A,   24,    2,   2,  14,   0,    2,     0,  1)
0153 MUX_CFG("W11_1610_MPUIO9",  10,   15,    1,   3,   8,   0,    3,     0,  1)
0154 MUX_CFG("V10_1610_MPUIO10",  A,   24,    1,   2,  14,   0,    2,     0,  1)
0155 MUX_CFG("W10_1610_MPUIO11",  A,   18,    2,   2,  11,   0,    2,     0,  1)
0156 MUX_CFG("E20_1610_MPUIO13",  3,   21,    1,   0,   7,   0,    0,     0,  1)
0157 MUX_CFG("U20_1610_MPUIO14",  9,    6,    6,   0,  30,   0,    0,     0,  1)
0158 MUX_CFG("E19_1610_MPUIO15",  3,   18,    1,   0,   6,   0,    0,     0,  1)
0159 
0160 /* MCBSP2 */
0161 MUX_CFG("MCBSP2_CLKR",       C,    6,    0,   2,  27,   1,   NA,     0,  1)
0162 MUX_CFG("MCBSP2_CLKX",       C,    9,    0,   2,  29,   1,   NA,     0,  1)
0163 MUX_CFG("MCBSP2_DR",         C,    0,    0,   2,  26,   1,   NA,     0,  1)
0164 MUX_CFG("MCBSP2_DX",         C,   15,    0,   2,  31,   1,   NA,     0,  1)
0165 MUX_CFG("MCBSP2_FSR",        C,   12,    0,   2,  30,   1,   NA,     0,  1)
0166 MUX_CFG("MCBSP2_FSX",        C,    3,    0,   2,  27,   1,   NA,     0,  1)
0167 
0168 /* MCBSP3 NOTE: Mode must 1 for clock */
0169 MUX_CFG("MCBSP3_CLKX",       9,    3,    1,   1,  29,   0,   NA,     0,  1)
0170 
0171 /* Misc ballouts */
0172 MUX_CFG("BALLOUT_V8_ARMIO3",     B,   18,    0,   2,  25,   1,   NA,     0,  1)
0173 MUX_CFG("N20_HDQ",       6,   18,    1,   1,   4,   0,    1,     4,  0)
0174 
0175 /* OMAP-1610 MMC2 */
0176 MUX_CFG("W8_1610_MMC2_DAT0",     B,   21,    6,   2,  23,   1,    2,     1,  1)
0177 MUX_CFG("V8_1610_MMC2_DAT1",     B,   27,    6,   2,  25,   1,    2,     1,  1)
0178 MUX_CFG("W15_1610_MMC2_DAT2",    9,   12,    6,   2,   5,   1,    2,     1,  1)
0179 MUX_CFG("R10_1610_MMC2_DAT3",    B,   18,    6,   2,  22,   1,    2,     1,  1)
0180 MUX_CFG("Y10_1610_MMC2_CLK",     B,    3,    6,   2,  17,   0,    2,     0,  1)
0181 MUX_CFG("Y8_1610_MMC2_CMD",  B,   24,    6,   2,  24,   1,    2,     1,  1)
0182 MUX_CFG("V9_1610_MMC2_CMDDIR",   B,   12,    6,   2,  20,   0,    2,     1,  1)
0183 MUX_CFG("V5_1610_MMC2_DATDIR0",  B,   15,    6,   2,  21,   0,    2,     1,  1)
0184 MUX_CFG("W19_1610_MMC2_DATDIR1", 8,   15,    6,   1,  23,   0,    1,     1,  1)
0185 MUX_CFG("R18_1610_MMC2_CLKIN",   7,    9,    6,   1,  11,   0,    1,    11,  1)
0186 
0187 /* OMAP-1610 External Trace Interface */
0188 MUX_CFG("M19_1610_ETM_PSTAT0",   5,   27,    1,   0,  29,   0,    0,     0,  1)
0189 MUX_CFG("L15_1610_ETM_PSTAT1",   5,   24,    1,   0,  28,   0,    0,     0,  1)
0190 MUX_CFG("L18_1610_ETM_PSTAT2",   5,   21,    1,   0,  27,   0,    0,     0,  1)
0191 MUX_CFG("L19_1610_ETM_D0",   5,   18,    1,   0,  26,   0,    0,     0,  1)
0192 MUX_CFG("J19_1610_ETM_D6",   5,    0,    1,   0,  20,   0,    0,     0,  1)
0193 MUX_CFG("J18_1610_ETM_D7",   5,   27,    1,   0,  19,   0,    0,     0,  1)
0194 
0195 /* OMAP16XX GPIO */
0196 MUX_CFG("P20_1610_GPIO4",    6,   27,    0,   1,   7,   0,    1,     1,  1)
0197 MUX_CFG("V9_1610_GPIO7",     B,   12,    1,   2,  20,   0,    2,     1,  1)
0198 MUX_CFG("W8_1610_GPIO9",     B,   21,    0,   2,  23,   0,    2,     1,  1)
0199 MUX_CFG("N20_1610_GPIO11",       6,   18,    0,   1,   4,   0,    1,     1,  1)
0200 MUX_CFG("N19_1610_GPIO13",   6,   12,    0,   1,   2,   0,    1,     1,  1)
0201 MUX_CFG("P10_1610_GPIO22",   C,    0,    7,   2,  26,   0,    2,     1,  1)
0202 MUX_CFG("V5_1610_GPIO24",    B,   15,    7,   2,  21,   0,    2,     1,  1)
0203 MUX_CFG("AA20_1610_GPIO_41",     9,    9,    7,   1,  31,   0,    1,     1,  1)
0204 MUX_CFG("W19_1610_GPIO48",   8,   15,    7,   1,  23,   1,    1,     0,  1)
0205 MUX_CFG("M7_1610_GPIO62",   10,    0,    0,   4,  24,   0,    4,     0,  1)
0206 MUX_CFG("V14_16XX_GPIO37",   9,   18,    7,   2,   2,   0,    2,     2,  0)
0207 MUX_CFG("R9_16XX_GPIO18",    C,   18,    7,   3,   0,   0,    3,     0,  0)
0208 MUX_CFG("L14_16XX_GPIO49",   6,    3,    7,   0,  31,   0,    0,    31,  0)
0209 
0210 /* OMAP-1610 uWire */
0211 MUX_CFG("V19_1610_UWIRE_SCLK",   8,    6,    0,   1,  20,   0,    1,     1,  1)
0212 MUX_CFG("U18_1610_UWIRE_SDI",    8,    0,    0,   1,  18,   0,    1,     1,  1)
0213 MUX_CFG("W21_1610_UWIRE_SDO",    8,    3,    0,   1,  19,   0,    1,     1,  1)
0214 MUX_CFG("N14_1610_UWIRE_CS0",    8,    9,    1,   1,  21,   0,    1,     1,  1)
0215 MUX_CFG("P15_1610_UWIRE_CS3",    8,   12,    1,   1,  22,   0,    1,     1,  1)
0216 MUX_CFG("N15_1610_UWIRE_CS1",    7,   18,    2,   1,  14,   0,   NA,     0,  1)
0217 
0218 /* OMAP-1610 SPI */
0219 MUX_CFG("U19_1610_SPIF_SCK",     7,    21,   6,   1,  15,   0,    1,     1,  1)
0220 MUX_CFG("U18_1610_SPIF_DIN",     8,    0,    6,   1,  18,   1,    1,     0,  1)
0221 MUX_CFG("P20_1610_SPIF_DIN",     6,    27,   4,   1,   7,   1,    1,     0,  1)
0222 MUX_CFG("W21_1610_SPIF_DOUT",    8,    3,    6,   1,  19,   0,    1,     0,  1)
0223 MUX_CFG("R18_1610_SPIF_DOUT",    7,    9,    3,   1,  11,   0,    1,     0,  1)
0224 MUX_CFG("N14_1610_SPIF_CS0",     8,    9,    6,   1,  21,   0,    1,     1,  1)
0225 MUX_CFG("N15_1610_SPIF_CS1",     7,    18,   6,   1,  14,   0,    1,     1,  1)
0226 MUX_CFG("T19_1610_SPIF_CS2",     7,    15,   4,   1,  13,   0,    1,     1,  1)
0227 MUX_CFG("P15_1610_SPIF_CS3",     8,    12,   3,   1,  22,   0,    1,     1,  1)
0228 
0229 /* OMAP-1610 Flash */
0230 MUX_CFG("L3_1610_FLASH_CS2B_OE",10,    6,    1,  NA,   0,   0,   NA,     0,  1)
0231 MUX_CFG("M8_1610_FLASH_CS2B_WE",10,    3,    1,  NA,   0,   0,   NA,     0,  1)
0232 
0233 /* First MMC interface, same on 1510, 1610 and 1710 */
0234 MUX_CFG("MMC_CMD",       A,   27,    0,   2,  15,   1,    2,     1,  1)
0235 MUX_CFG("MMC_DAT1",      A,   24,    0,   2,  14,   1,    2,     1,  1)
0236 MUX_CFG("MMC_DAT2",      A,   18,    0,   2,  12,   1,    2,     1,  1)
0237 MUX_CFG("MMC_DAT0",      B,    0,    0,   2,  16,   1,    2,     1,  1)
0238 MUX_CFG("MMC_CLK",       A,   21,    0,  NA,   0,   0,   NA,     0,  1)
0239 MUX_CFG("MMC_DAT3",     10,   15,    0,   3,   8,   1,    3,     1,  1)
0240 MUX_CFG("M15_1710_MMC_CLKI",     6,   21,    2,   0,   0,   0,   NA,     0,  1)
0241 MUX_CFG("P19_1710_MMC_CMDDIR",   6,   24,    6,   0,   0,   0,   NA,     0,  1)
0242 MUX_CFG("P20_1710_MMC_DATDIR0",  6,   27,    5,   0,   0,   0,   NA,     0,  1)
0243 
0244 /* OMAP-1610 USB0 alternate configuration */
0245 MUX_CFG("W9_USB0_TXEN",      B,   9,     5,   2,  19,   0,    2,     0,  1)
0246 MUX_CFG("AA9_USB0_VP",       B,   6,     5,   2,  18,   0,    2,     0,  1)
0247 MUX_CFG("Y5_USB0_RCV",       C,  21,     5,   3,   1,   0,    1,     0,  1)
0248 MUX_CFG("R9_USB0_VM",        C,  18,     5,   3,   0,   0,    3,     0,  1)
0249 MUX_CFG("V6_USB0_TXD",       C,  27,     5,   3,   3,   0,    3,     0,  1)
0250 MUX_CFG("W5_USB0_SE0",       C,  24,     5,   3,   2,   0,    3,     0,  1)
0251 MUX_CFG("V9_USB0_SPEED",     B,  12,     5,   2,  20,   0,    2,     0,  1)
0252 MUX_CFG("Y10_USB0_SUSP",     B,   3,     5,   2,  17,   0,    2,     0,  1)
0253 
0254 /* USB2 interface */
0255 MUX_CFG("W9_USB2_TXEN",      B,   9,     1,  NA,   0,   0,   NA,     0,  1)
0256 MUX_CFG("AA9_USB2_VP",       B,   6,     1,  NA,   0,   0,   NA,     0,  1)
0257 MUX_CFG("Y5_USB2_RCV",       C,  21,     1,  NA,   0,   0,   NA,     0,  1)
0258 MUX_CFG("R9_USB2_VM",        C,  18,     1,  NA,   0,   0,   NA,     0,  1)
0259 MUX_CFG("V6_USB2_TXD",       C,  27,     2,  NA,   0,   0,   NA,     0,  1)
0260 MUX_CFG("W5_USB2_SE0",       C,  24,     2,  NA,   0,   0,   NA,     0,  1)
0261 
0262 /* 16XX UART */
0263 MUX_CFG("R13_1610_UART1_TX",     A,  12,     6,   2,  10,   0,    2,    10,  1)
0264 MUX_CFG("V14_16XX_UART1_RX",     9,  18,     0,   2,   2,   0,    2,     2,  1)
0265 MUX_CFG("R14_1610_UART1_CTS",    9,  15,     0,   2,   1,   0,    2,     1,  1)
0266 MUX_CFG("AA15_1610_UART1_RTS",   9,  12,     1,   2,   0,   0,    2,     0,  1)
0267 MUX_CFG("R9_16XX_UART2_RX",  C,  18,     0,   3,   0,   0,    3,     0,  1)
0268 MUX_CFG("L14_16XX_UART3_RX",     6,   3,     0,   0,  31,   0,    0,    31,  1)
0269 
0270 /* I2C interface */
0271 MUX_CFG("I2C_SCL",       7,  24,     0,  NA,   0,   0,   NA,     0,  0)
0272 MUX_CFG("I2C_SDA",       7,  27,     0,  NA,   0,   0,   NA,     0,  0)
0273 
0274 /* Keypad */
0275 MUX_CFG("F18_1610_KBC0",     3,  15,     0,   0,   5,   1,    0,     0,  0)
0276 MUX_CFG("D20_1610_KBC1",     3,  12,     0,   0,   4,   1,    0,     0,  0)
0277 MUX_CFG("D19_1610_KBC2",     3,   9,     0,   0,   3,   1,    0,     0,  0)
0278 MUX_CFG("E18_1610_KBC3",     3,   6,     0,   0,   2,   1,    0,     0,  0)
0279 MUX_CFG("C21_1610_KBC4",     3,   3,     0,   0,   1,   1,    0,     0,  0)
0280 MUX_CFG("G18_1610_KBR0",     4,   0,     0,   0,   10,  1,    0,     1,  0)
0281 MUX_CFG("F19_1610_KBR1",     3,   27,    0,   0,   9,   1,    0,     1,  0)
0282 MUX_CFG("H14_1610_KBR2",     3,   24,    0,   0,   8,   1,    0,     1,  0)
0283 MUX_CFG("E20_1610_KBR3",     3,   21,    0,   0,   7,   1,    0,     1,  0)
0284 MUX_CFG("E19_1610_KBR4",     3,   18,    0,   0,   6,   1,    0,     1,  0)
0285 MUX_CFG("N19_1610_KBR5",     6,  12,     1,   1,   2,   1,    1,     1,  0)
0286 
0287 /* Power management */
0288 MUX_CFG("T20_1610_LOW_PWR",  7,   12,    1,   NA,   0,   0,   NA,    0,  0)
0289 
0290 /* MCLK Settings */
0291 MUX_CFG("V5_1710_MCLK_ON",   B,   15,    0,   NA,   0,   0,   NA,    0,  0)
0292 MUX_CFG("V5_1710_MCLK_OFF",  B,   15,    6,   NA,   0,   0,   NA,    0,  0)
0293 MUX_CFG("R10_1610_MCLK_ON",  B,   18,    0,   NA,  22,   0,   NA,    1,  0)
0294 MUX_CFG("R10_1610_MCLK_OFF",     B,   18,    6,   2,   22,   1,   2,     1,  1)
0295 
0296 /* CompactFlash controller, conflicts with MMC1 */
0297 MUX_CFG("P11_1610_CF_CD2",   A,   27,    3,   2,   15,   1,   2,     1,  1)
0298 MUX_CFG("R11_1610_CF_IOIS16",    B,    0,    3,   2,   16,   1,   2,     1,  1)
0299 MUX_CFG("V10_1610_CF_IREQ",  A,   24,    3,   2,   14,   0,   2,     0,  1)
0300 MUX_CFG("W10_1610_CF_RESET",     A,   18,    3,   2,   12,   1,   2,     1,  1)
0301 MUX_CFG("W11_1610_CF_CD1",  10,   15,    3,   3,    8,   1,   3,     1,  1)
0302 
0303 /* parallel camera */
0304 MUX_CFG("J15_1610_CAM_LCLK",     4,   24,    0,   0,  18,   1,    0,     0,  0)
0305 MUX_CFG("J18_1610_CAM_D7",   4,   27,    0,   0,  19,   1,    0,     0,  0)
0306 MUX_CFG("J19_1610_CAM_D6",   5,    0,    0,   0,  20,   1,    0,     0,  0)
0307 MUX_CFG("J14_1610_CAM_D5",   5,    3,    0,   0,  21,   1,    0,     0,  0)
0308 MUX_CFG("K18_1610_CAM_D4",   5,    6,    0,   0,  22,   1,    0,     0,  0)
0309 MUX_CFG("K19_1610_CAM_D3",   5,    9,    0,   0,  23,   1,    0,     0,  0)
0310 MUX_CFG("K15_1610_CAM_D2",   5,   12,    0,   0,  24,   1,    0,     0,  0)
0311 MUX_CFG("K14_1610_CAM_D1",   5,   15,    0,   0,  25,   1,    0,     0,  0)
0312 MUX_CFG("L19_1610_CAM_D0",   5,   18,    0,   0,  26,   1,    0,     0,  0)
0313 MUX_CFG("L18_1610_CAM_VS",   5,   21,    0,   0,  27,   1,    0,     0,  0)
0314 MUX_CFG("L15_1610_CAM_HS",   5,   24,    0,   0,  28,   1,    0,     0,  0)
0315 MUX_CFG("M19_1610_CAM_RSTZ",     5,   27,    0,   0,  29,   0,    0,     0,  0)
0316 MUX_CFG("Y15_1610_CAM_OUTCLK",   A,    0,    6,   2,   6,   0,    2,     0,  0)
0317 
0318 /* serial camera */
0319 MUX_CFG("H19_1610_CAM_EXCLK",    4,   21,    0,   0,  17,   0,    0,     0,  0)
0320     /* REVISIT 5912 spec sez CCP_* can't pullup or pulldown ... ? */
0321 MUX_CFG("Y12_1610_CCP_CLKP",     8,   18,    6,   1,  24,   1,    1,     0,  0)
0322 MUX_CFG("W13_1610_CCP_CLKM",     9,    0,    6,   1,  28,   1,    1,     0,  0)
0323 MUX_CFG("W14_1610_CCP_DATAP",    9,   24,    6,   2,   4,   1,    2,     0,  0)
0324 MUX_CFG("Y14_1610_CCP_DATAM",    9,   21,    6,   2,   3,   1,    2,     0,  0)
0325 };
0326 #define OMAP1XXX_PINS_SZ    ARRAY_SIZE(omap1xxx_pins)
0327 #else
0328 #define omap1xxx_pins       NULL
0329 #define OMAP1XXX_PINS_SZ    0
0330 #endif  /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
0331 
0332 static int omap1_cfg_reg(const struct pin_config *cfg)
0333 {
0334     static DEFINE_SPINLOCK(mux_spin_lock);
0335     unsigned long flags;
0336     unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
0337         pull_orig = 0, pull = 0;
0338     unsigned int mask, warn = 0;
0339 
0340     /* Check the mux register in question */
0341     if (cfg->mux_reg) {
0342         unsigned    tmp1, tmp2;
0343 
0344         spin_lock_irqsave(&mux_spin_lock, flags);
0345         reg_orig = omap_readl(cfg->mux_reg);
0346 
0347         /* The mux registers always seem to be 3 bits long */
0348         mask = (0x7 << cfg->mask_offset);
0349         tmp1 = reg_orig & mask;
0350         reg = reg_orig & ~mask;
0351 
0352         tmp2 = (cfg->mask << cfg->mask_offset);
0353         reg |= tmp2;
0354 
0355         if (tmp1 != tmp2)
0356             warn = 1;
0357 
0358         omap_writel(reg, cfg->mux_reg);
0359         spin_unlock_irqrestore(&mux_spin_lock, flags);
0360     }
0361 
0362     /* Check for pull up or pull down selection on 1610 */
0363     if (!cpu_is_omap15xx()) {
0364         if (cfg->pu_pd_reg && cfg->pull_val) {
0365             spin_lock_irqsave(&mux_spin_lock, flags);
0366             pu_pd_orig = omap_readl(cfg->pu_pd_reg);
0367             mask = 1 << cfg->pull_bit;
0368 
0369             if (cfg->pu_pd_val) {
0370                 if (!(pu_pd_orig & mask))
0371                     warn = 1;
0372                 /* Use pull up */
0373                 pu_pd = pu_pd_orig | mask;
0374             } else {
0375                 if (pu_pd_orig & mask)
0376                     warn = 1;
0377                 /* Use pull down */
0378                 pu_pd = pu_pd_orig & ~mask;
0379             }
0380             omap_writel(pu_pd, cfg->pu_pd_reg);
0381             spin_unlock_irqrestore(&mux_spin_lock, flags);
0382         }
0383     }
0384 
0385     /* Check for an associated pull down register */
0386     if (cfg->pull_reg) {
0387         spin_lock_irqsave(&mux_spin_lock, flags);
0388         pull_orig = omap_readl(cfg->pull_reg);
0389         mask = 1 << cfg->pull_bit;
0390 
0391         if (cfg->pull_val) {
0392             if (pull_orig & mask)
0393                 warn = 1;
0394             /* Low bit = pull enabled */
0395             pull = pull_orig & ~mask;
0396         } else {
0397             if (!(pull_orig & mask))
0398                 warn = 1;
0399             /* High bit = pull disabled */
0400             pull = pull_orig | mask;
0401         }
0402 
0403         omap_writel(pull, cfg->pull_reg);
0404         spin_unlock_irqrestore(&mux_spin_lock, flags);
0405     }
0406 
0407     if (warn) {
0408 #ifdef CONFIG_OMAP_MUX_WARNINGS
0409         printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
0410 #endif
0411     }
0412 
0413 #ifdef CONFIG_OMAP_MUX_DEBUG
0414     if (cfg->debug || warn) {
0415         printk("MUX: Setting register %s\n", cfg->name);
0416         printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
0417                cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
0418 
0419         if (!cpu_is_omap15xx()) {
0420             if (cfg->pu_pd_reg && cfg->pull_val) {
0421                 printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
0422                        cfg->pu_pd_name, cfg->pu_pd_reg,
0423                        pu_pd_orig, pu_pd);
0424             }
0425         }
0426 
0427         if (cfg->pull_reg)
0428             printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
0429                    cfg->pull_name, cfg->pull_reg, pull_orig, pull);
0430     }
0431 #endif
0432 
0433 #ifdef CONFIG_OMAP_MUX_WARNINGS
0434     return warn ? -ETXTBSY : 0;
0435 #else
0436     return 0;
0437 #endif
0438 }
0439 
0440 static struct omap_mux_cfg *mux_cfg;
0441 
0442 int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
0443 {
0444     if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
0445             || !arch_mux_cfg->cfg_reg) {
0446         printk(KERN_ERR "Invalid pin table\n");
0447         return -EINVAL;
0448     }
0449 
0450     mux_cfg = arch_mux_cfg;
0451 
0452     return 0;
0453 }
0454 
0455 /*
0456  * Sets the Omap MUX and PULL_DWN registers based on the table
0457  */
0458 int omap_cfg_reg(const unsigned long index)
0459 {
0460     struct pin_config *reg;
0461 
0462     if (!cpu_class_is_omap1()) {
0463         printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
0464                 index);
0465         WARN_ON(1);
0466         return -EINVAL;
0467     }
0468 
0469     if (mux_cfg == NULL) {
0470         printk(KERN_ERR "Pin mux table not initialized\n");
0471         return -ENODEV;
0472     }
0473 
0474     if (index >= mux_cfg->size) {
0475         printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
0476                index, mux_cfg->size);
0477         dump_stack();
0478         return -ENODEV;
0479     }
0480 
0481     reg = &mux_cfg->pins[index];
0482 
0483     if (!mux_cfg->cfg_reg)
0484         return -ENODEV;
0485 
0486     return mux_cfg->cfg_reg(reg);
0487 }
0488 EXPORT_SYMBOL(omap_cfg_reg);
0489 
0490 int __init omap1_mux_init(void)
0491 {
0492     if (cpu_is_omap7xx()) {
0493         arch_mux_cfg.pins   = omap7xx_pins;
0494         arch_mux_cfg.size   = OMAP7XX_PINS_SZ;
0495         arch_mux_cfg.cfg_reg    = omap1_cfg_reg;
0496     }
0497 
0498     if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
0499         arch_mux_cfg.pins   = omap1xxx_pins;
0500         arch_mux_cfg.size   = OMAP1XXX_PINS_SZ;
0501         arch_mux_cfg.cfg_reg    = omap1_cfg_reg;
0502     }
0503 
0504     return omap_mux_register(&arch_mux_cfg);
0505 }
0506 
0507 #else
0508 #define omap_mux_init() do {} while(0)
0509 #define omap_cfg_reg(x) do {} while(0)
0510 #endif  /* CONFIG_OMAP_MUX */
0511
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