arm/mach-omap1/irqs.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  Copyright (C) Greg Lonnon 2001
0004  *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
0005  *
0006  * Copyright (C) 2009 Texas Instruments
0007  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
0008  *
0009  * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
0010  *   are different.
0011  */
0012
0013 #ifndef __ASM_ARCH_OMAP15XX_IRQS_H
0014 #define __ASM_ARCH_OMAP15XX_IRQS_H
0015
0016 /*
0017  * IRQ numbers for interrupt handler 1
0018  *
0019  * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
0020  *
0021  */
0022 #define INT_CAMERA      (NR_IRQS_LEGACY + 1)
0023 #define INT_FIQ         (NR_IRQS_LEGACY + 3)
0024 #define INT_RTDX        (NR_IRQS_LEGACY + 6)
0025 #define INT_DSP_MMU_ABORT   (NR_IRQS_LEGACY + 7)
0026 #define INT_HOST        (NR_IRQS_LEGACY + 8)
0027 #define INT_ABORT       (NR_IRQS_LEGACY + 9)
0028 #define INT_BRIDGE_PRIV     (NR_IRQS_LEGACY + 13)
0029 #define INT_GPIO_BANK1      (NR_IRQS_LEGACY + 14)
0030 #define INT_UART3       (NR_IRQS_LEGACY + 15)
0031 #define INT_TIMER3      (NR_IRQS_LEGACY + 16)
0032 #define INT_DMA_CH0_6       (NR_IRQS_LEGACY + 19)
0033 #define INT_DMA_CH1_7       (NR_IRQS_LEGACY + 20)
0034 #define INT_DMA_CH2_8       (NR_IRQS_LEGACY + 21)
0035 #define INT_DMA_CH3     (NR_IRQS_LEGACY + 22)
0036 #define INT_DMA_CH4     (NR_IRQS_LEGACY + 23)
0037 #define INT_DMA_CH5     (NR_IRQS_LEGACY + 24)
0038 #define INT_TIMER1      (NR_IRQS_LEGACY + 26)
0039 #define INT_WD_TIMER        (NR_IRQS_LEGACY + 27)
0040 #define INT_BRIDGE_PUB      (NR_IRQS_LEGACY + 28)
0041 #define INT_TIMER2      (NR_IRQS_LEGACY + 30)
0042 #define INT_LCD_CTRL        (NR_IRQS_LEGACY + 31)
0043
0044 /*
0045  * OMAP-1510 specific IRQ numbers for interrupt handler 1
0046  */
0047 #define INT_1510_IH2_IRQ    (NR_IRQS_LEGACY + 0)
0048 #define INT_1510_RES2       (NR_IRQS_LEGACY + 2)
0049 #define INT_1510_SPI_TX     (NR_IRQS_LEGACY + 4)
0050 #define INT_1510_SPI_RX     (NR_IRQS_LEGACY + 5)
0051 #define INT_1510_DSP_MAILBOX1   (NR_IRQS_LEGACY + 10)
0052 #define INT_1510_DSP_MAILBOX2   (NR_IRQS_LEGACY + 11)
0053 #define INT_1510_RES12      (NR_IRQS_LEGACY + 12)
0054 #define INT_1510_LB_MMU     (NR_IRQS_LEGACY + 17)
0055 #define INT_1510_RES18      (NR_IRQS_LEGACY + 18)
0056 #define INT_1510_LOCAL_BUS  (NR_IRQS_LEGACY + 29)
0057
0058 /*
0059  * OMAP-1610 specific IRQ numbers for interrupt handler 1
0060  */
0061 #define INT_1610_IH2_IRQ    INT_1510_IH2_IRQ
0062 #define INT_1610_IH2_FIQ    (NR_IRQS_LEGACY + 2)
0063 #define INT_1610_McBSP2_TX  (NR_IRQS_LEGACY + 4)
0064 #define INT_1610_McBSP2_RX  (NR_IRQS_LEGACY + 5)
0065 #define INT_1610_DSP_MAILBOX1   (NR_IRQS_LEGACY + 10)
0066 #define INT_1610_DSP_MAILBOX2   (NR_IRQS_LEGACY + 11)
0067 #define INT_1610_LCD_LINE   (NR_IRQS_LEGACY + 12)
0068 #define INT_1610_GPTIMER1   (NR_IRQS_LEGACY + 17)
0069 #define INT_1610_GPTIMER2   (NR_IRQS_LEGACY + 18)
0070 #define INT_1610_SSR_FIFO_0 (NR_IRQS_LEGACY + 29)
0071
0072 /*
0073  * OMAP-7xx specific IRQ numbers for interrupt handler 1
0074  */
0075 #define INT_7XX_IH2_FIQ     (NR_IRQS_LEGACY + 0)
0076 #define INT_7XX_IH2_IRQ     (NR_IRQS_LEGACY + 1)
0077 #define INT_7XX_USB_NON_ISO (NR_IRQS_LEGACY + 2)
0078 #define INT_7XX_USB_ISO     (NR_IRQS_LEGACY + 3)
0079 #define INT_7XX_ICR     (NR_IRQS_LEGACY + 4)
0080 #define INT_7XX_EAC     (NR_IRQS_LEGACY + 5)
0081 #define INT_7XX_GPIO_BANK1  (NR_IRQS_LEGACY + 6)
0082 #define INT_7XX_GPIO_BANK2  (NR_IRQS_LEGACY + 7)
0083 #define INT_7XX_GPIO_BANK3  (NR_IRQS_LEGACY + 8)
0084 #define INT_7XX_McBSP2TX    (NR_IRQS_LEGACY + 10)
0085 #define INT_7XX_McBSP2RX    (NR_IRQS_LEGACY + 11)
0086 #define INT_7XX_McBSP2RX_OVF    (NR_IRQS_LEGACY + 12)
0087 #define INT_7XX_LCD_LINE    (NR_IRQS_LEGACY + 14)
0088 #define INT_7XX_GSM_PROTECT (NR_IRQS_LEGACY + 15)
0089 #define INT_7XX_TIMER3      (NR_IRQS_LEGACY + 16)
0090 #define INT_7XX_GPIO_BANK5  (NR_IRQS_LEGACY + 17)
0091 #define INT_7XX_GPIO_BANK6  (NR_IRQS_LEGACY + 18)
0092 #define INT_7XX_SPGIO_WR    (NR_IRQS_LEGACY + 29)
0093
0094 /*
0095  * IRQ numbers for interrupt handler 2
0096  *
0097  * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
0098  */
0099 #define IH2_BASE        (NR_IRQS_LEGACY + 32)
0100
0101 #define INT_KEYBOARD        (1 + IH2_BASE)
0102 #define INT_uWireTX     (2 + IH2_BASE)
0103 #define INT_uWireRX     (3 + IH2_BASE)
0104 #define INT_I2C         (4 + IH2_BASE)
0105 #define INT_MPUIO       (5 + IH2_BASE)
0106 #define INT_USB_HHC_1       (6 + IH2_BASE)
0107 #define INT_McBSP3TX        (10 + IH2_BASE)
0108 #define INT_McBSP3RX        (11 + IH2_BASE)
0109 #define INT_McBSP1TX        (12 + IH2_BASE)
0110 #define INT_McBSP1RX        (13 + IH2_BASE)
0111 #define INT_UART1       (14 + IH2_BASE)
0112 #define INT_UART2       (15 + IH2_BASE)
0113 #define INT_BT_MCSI1TX      (16 + IH2_BASE)
0114 #define INT_BT_MCSI1RX      (17 + IH2_BASE)
0115 #define INT_SOSSI_MATCH     (19 + IH2_BASE)
0116 #define INT_USB_W2FC        (20 + IH2_BASE)
0117 #define INT_1WIRE       (21 + IH2_BASE)
0118 #define INT_OS_TIMER        (22 + IH2_BASE)
0119 #define INT_MMC         (23 + IH2_BASE)
0120 #define INT_GAUGE_32K       (24 + IH2_BASE)
0121 #define INT_RTC_TIMER       (25 + IH2_BASE)
0122 #define INT_RTC_ALARM       (26 + IH2_BASE)
0123 #define INT_MEM_STICK       (27 + IH2_BASE)
0124
0125 /*
0126  * OMAP-1510 specific IRQ numbers for interrupt handler 2
0127  */
0128 #define INT_1510_DSP_MMU    (28 + IH2_BASE)
0129 #define INT_1510_COM_SPI_RO (31 + IH2_BASE)
0130
0131 /*
0132  * OMAP-1610 specific IRQ numbers for interrupt handler 2
0133  */
0134 #define INT_1610_FAC        (0 + IH2_BASE)
0135 #define INT_1610_USB_HHC_2  (7 + IH2_BASE)
0136 #define INT_1610_USB_OTG    (8 + IH2_BASE)
0137 #define INT_1610_SoSSI      (9 + IH2_BASE)
0138 #define INT_1610_SoSSI_MATCH    (19 + IH2_BASE)
0139 #define INT_1610_DSP_MMU    (28 + IH2_BASE)
0140 #define INT_1610_McBSP2RX_OF    (31 + IH2_BASE)
0141 #define INT_1610_STI        (32 + IH2_BASE)
0142 #define INT_1610_STI_WAKEUP (33 + IH2_BASE)
0143 #define INT_1610_GPTIMER3   (34 + IH2_BASE)
0144 #define INT_1610_GPTIMER4   (35 + IH2_BASE)
0145 #define INT_1610_GPTIMER5   (36 + IH2_BASE)
0146 #define INT_1610_GPTIMER6   (37 + IH2_BASE)
0147 #define INT_1610_GPTIMER7   (38 + IH2_BASE)
0148 #define INT_1610_GPTIMER8   (39 + IH2_BASE)
0149 #define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
0150 #define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
0151 #define INT_1610_MMC2       (42 + IH2_BASE)
0152 #define INT_1610_CF     (43 + IH2_BASE)
0153 #define INT_1610_WAKE_UP_REQ    (46 + IH2_BASE)
0154 #define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
0155 #define INT_1610_SPI        (49 + IH2_BASE)
0156 #define INT_1610_DMA_CH6    (53 + IH2_BASE)
0157 #define INT_1610_DMA_CH7    (54 + IH2_BASE)
0158 #define INT_1610_DMA_CH8    (55 + IH2_BASE)
0159 #define INT_1610_DMA_CH9    (56 + IH2_BASE)
0160 #define INT_1610_DMA_CH10   (57 + IH2_BASE)
0161 #define INT_1610_DMA_CH11   (58 + IH2_BASE)
0162 #define INT_1610_DMA_CH12   (59 + IH2_BASE)
0163 #define INT_1610_DMA_CH13   (60 + IH2_BASE)
0164 #define INT_1610_DMA_CH14   (61 + IH2_BASE)
0165 #define INT_1610_DMA_CH15   (62 + IH2_BASE)
0166 #define INT_1610_NAND       (63 + IH2_BASE)
0167 #define INT_1610_SHA1MD5    (91 + IH2_BASE)
0168
0169 /*
0170  * OMAP-7xx specific IRQ numbers for interrupt handler 2
0171  */
0172 #define INT_7XX_HW_ERRORS   (0 + IH2_BASE)
0173 #define INT_7XX_NFIQ_PWR_FAIL   (1 + IH2_BASE)
0174 #define INT_7XX_CFCD        (2 + IH2_BASE)
0175 #define INT_7XX_CFIREQ      (3 + IH2_BASE)
0176 #define INT_7XX_I2C     (4 + IH2_BASE)
0177 #define INT_7XX_PCC     (5 + IH2_BASE)
0178 #define INT_7XX_MPU_EXT_NIRQ    (6 + IH2_BASE)
0179 #define INT_7XX_SPI_100K_1  (7 + IH2_BASE)
0180 #define INT_7XX_SYREN_SPI   (8 + IH2_BASE)
0181 #define INT_7XX_VLYNQ       (9 + IH2_BASE)
0182 #define INT_7XX_GPIO_BANK4  (10 + IH2_BASE)
0183 #define INT_7XX_McBSP1TX    (11 + IH2_BASE)
0184 #define INT_7XX_McBSP1RX    (12 + IH2_BASE)
0185 #define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
0186 #define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
0187 #define INT_7XX_UART_MODEM_1    (15 + IH2_BASE)
0188 #define INT_7XX_MCSI        (16 + IH2_BASE)
0189 #define INT_7XX_uWireTX     (17 + IH2_BASE)
0190 #define INT_7XX_uWireRX     (18 + IH2_BASE)
0191 #define INT_7XX_SMC_CD      (19 + IH2_BASE)
0192 #define INT_7XX_SMC_IREQ    (20 + IH2_BASE)
0193 #define INT_7XX_HDQ_1WIRE   (21 + IH2_BASE)
0194 #define INT_7XX_TIMER32K    (22 + IH2_BASE)
0195 #define INT_7XX_MMC_SDIO    (23 + IH2_BASE)
0196 #define INT_7XX_UPLD        (24 + IH2_BASE)
0197 #define INT_7XX_USB_HHC_1   (27 + IH2_BASE)
0198 #define INT_7XX_USB_HHC_2   (28 + IH2_BASE)
0199 #define INT_7XX_USB_GENI    (29 + IH2_BASE)
0200 #define INT_7XX_USB_OTG     (30 + IH2_BASE)
0201 #define INT_7XX_CAMERA_IF   (31 + IH2_BASE)
0202 #define INT_7XX_RNG     (32 + IH2_BASE)
0203 #define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
0204 #define INT_7XX_DBB_RF_EN   (34 + IH2_BASE)
0205 #define INT_7XX_MPUIO_KEYPAD    (35 + IH2_BASE)
0206 #define INT_7XX_SHA1_MD5    (36 + IH2_BASE)
0207 #define INT_7XX_SPI_100K_2  (37 + IH2_BASE)
0208 #define INT_7XX_RNG_IDLE    (38 + IH2_BASE)
0209 #define INT_7XX_MPUIO       (39 + IH2_BASE)
0210 #define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF    (40 + IH2_BASE)
0211 #define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
0212 #define INT_7XX_LLPC_OE_RISING  (42 + IH2_BASE)
0213 #define INT_7XX_LLPC_VSYNC  (43 + IH2_BASE)
0214 #define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
0215 #define INT_7XX_DMA_CH6     (53 + IH2_BASE)
0216 #define INT_7XX_DMA_CH7     (54 + IH2_BASE)
0217 #define INT_7XX_DMA_CH8     (55 + IH2_BASE)
0218 #define INT_7XX_DMA_CH9     (56 + IH2_BASE)
0219 #define INT_7XX_DMA_CH10    (57 + IH2_BASE)
0220 #define INT_7XX_DMA_CH11    (58 + IH2_BASE)
0221 #define INT_7XX_DMA_CH12    (59 + IH2_BASE)
0222 #define INT_7XX_DMA_CH13    (60 + IH2_BASE)
0223 #define INT_7XX_DMA_CH14    (61 + IH2_BASE)
0224 #define INT_7XX_DMA_CH15    (62 + IH2_BASE)
0225 #define INT_7XX_NAND        (63 + IH2_BASE)
0226
0227 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
0228  * 16 MPUIO lines */
0229 #define OMAP_MAX_GPIO_LINES 192
0230 #define IH_GPIO_BASE        (128 + IH2_BASE)
0231 #define IH_MPUIO_BASE       (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
0232 #define OMAP_IRQ_END        (IH_MPUIO_BASE + 16)
0233
0234 /* External FPGA handles interrupts on Innovator boards */
0235 #define OMAP_FPGA_IRQ_BASE  (OMAP_IRQ_END)
0236 #ifdef  CONFIG_MACH_OMAP_INNOVATOR
0237 #define OMAP_FPGA_NR_IRQS   24
0238 #else
0239 #define OMAP_FPGA_NR_IRQS   0
0240 #endif
0241 #define OMAP_FPGA_IRQ_END   (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
0242
0243 #define OMAP_IRQ_BIT(irq)   (1 << ((irq - NR_IRQS_LEGACY) % 32))
0244
0245 #ifdef CONFIG_FIQ
0246 #define FIQ_START       1024
0247 #endif
0248
0249 #endif