arm/mach-omap1/hardware.h

0001 /*
0002  * Hardware definitions for TI OMAP processors and boards
0003  *
0004  * NOTE: Please put device driver specific defines into a separate header
0005  *   file for each driver.
0006  *
0007  * Copyright (C) 2001 RidgeRun, Inc.
0008  * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
0009  *
0010  * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
0011  *                          and Dirk Behme <dirk.behme@de.bosch.com>
0012  *
0013  * This program is free software; you can redistribute it and/or modify it
0014  * under the terms of the GNU General Public License as published by the
0015  * Free Software Foundation; either version 2 of the License, or (at your
0016  * option) any later version.
0017  *
0018  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
0019  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
0020  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
0021  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
0022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0023  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
0024  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0025  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0026  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0027  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0028  *
0029  * You should have received a copy of the GNU General Public License along
0030  * with this program; if not, write to the Free Software Foundation, Inc.,
0031  * 675 Mass Ave, Cambridge, MA 02139, USA.
0032  */
0033
0034 #ifndef __ASM_ARCH_OMAP_HARDWARE_H
0035 #define __ASM_ARCH_OMAP_HARDWARE_H
0036
0037 #include <linux/sizes.h>
0038 #include <linux/soc/ti/omap1-io.h>
0039 #ifndef __ASSEMBLER__
0040 #include <asm/types.h>
0041 #include <linux/soc/ti/omap1-soc.h>
0042
0043 #include "tc.h"
0044
0045 /* Almost all documentation for chip and board memory maps assumes
0046  * BM is clear.  Most devel boards have a switch to control booting
0047  * from NOR flash (using external chipselect 3) rather than mask ROM,
0048  * which uses BM to interchange the physical CS0 and CS3 addresses.
0049  */
0050 static inline u32 omap_cs0m_phys(void)
0051 {
0052     return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
0053             ?  OMAP_CS3_PHYS : 0;
0054 }
0055
0056 static inline u32 omap_cs3_phys(void)
0057 {
0058     return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
0059             ? 0 : OMAP_CS3_PHYS;
0060 }
0061
0062 #endif  /* ifndef __ASSEMBLER__ */
0063
0064 #define OMAP1_IO_OFFSET     0x00f00000  /* Virtual IO = 0xff0b0000 */
0065 #define OMAP1_IO_ADDRESS(pa)    IOMEM((pa) - OMAP1_IO_OFFSET)
0066
0067 #include "serial.h"
0068
0069 /*
0070  * ---------------------------------------------------------------------------
0071  * Common definitions for all OMAP processors
0072  * NOTE: Put all processor or board specific parts to the special header
0073  *   files.
0074  * ---------------------------------------------------------------------------
0075  */
0076
0077 /*
0078  * ----------------------------------------------------------------------------
0079  * Timers
0080  * ----------------------------------------------------------------------------
0081  */
0082 #define OMAP_MPU_TIMER1_BASE    (0xfffec500)
0083 #define OMAP_MPU_TIMER2_BASE    (0xfffec600)
0084 #define OMAP_MPU_TIMER3_BASE    (0xfffec700)
0085 #define MPU_TIMER_FREE      (1 << 6)
0086 #define MPU_TIMER_CLOCK_ENABLE  (1 << 5)
0087 #define MPU_TIMER_AR        (1 << 1)
0088 #define MPU_TIMER_ST        (1 << 0)
0089
0090 /*
0091  * ---------------------------------------------------------------------------
0092  * Watchdog timer
0093  * ---------------------------------------------------------------------------
0094  */
0095
0096 /* Watchdog timer within the OMAP3.2 gigacell */
0097 #define OMAP_MPU_WATCHDOG_BASE  (0xfffec800)
0098 #define OMAP_WDT_TIMER      (OMAP_MPU_WATCHDOG_BASE + 0x0)
0099 #define OMAP_WDT_LOAD_TIM   (OMAP_MPU_WATCHDOG_BASE + 0x4)
0100 #define OMAP_WDT_READ_TIM   (OMAP_MPU_WATCHDOG_BASE + 0x4)
0101 #define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
0102
0103 /*
0104  * ---------------------------------------------------------------------------
0105  * Interrupts
0106  * ---------------------------------------------------------------------------
0107  */
0108 #ifdef CONFIG_ARCH_OMAP1
0109
0110 /*
0111  * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
0112  * or something similar.. -- PFM.
0113  */
0114
0115 #define OMAP_IH1_BASE       0xfffecb00
0116 #define OMAP_IH2_BASE       0xfffe0000
0117
0118 #define OMAP_IH1_ITR        (OMAP_IH1_BASE + 0x00)
0119 #define OMAP_IH1_MIR        (OMAP_IH1_BASE + 0x04)
0120 #define OMAP_IH1_SIR_IRQ    (OMAP_IH1_BASE + 0x10)
0121 #define OMAP_IH1_SIR_FIQ    (OMAP_IH1_BASE + 0x14)
0122 #define OMAP_IH1_CONTROL    (OMAP_IH1_BASE + 0x18)
0123 #define OMAP_IH1_ILR0       (OMAP_IH1_BASE + 0x1c)
0124 #define OMAP_IH1_ISR        (OMAP_IH1_BASE + 0x9c)
0125
0126 #define OMAP_IH2_ITR        (OMAP_IH2_BASE + 0x00)
0127 #define OMAP_IH2_MIR        (OMAP_IH2_BASE + 0x04)
0128 #define OMAP_IH2_SIR_IRQ    (OMAP_IH2_BASE + 0x10)
0129 #define OMAP_IH2_SIR_FIQ    (OMAP_IH2_BASE + 0x14)
0130 #define OMAP_IH2_CONTROL    (OMAP_IH2_BASE + 0x18)
0131 #define OMAP_IH2_ILR0       (OMAP_IH2_BASE + 0x1c)
0132 #define OMAP_IH2_ISR        (OMAP_IH2_BASE + 0x9c)
0133
0134 #define IRQ_ITR_REG_OFFSET  0x00
0135 #define IRQ_MIR_REG_OFFSET  0x04
0136 #define IRQ_SIR_IRQ_REG_OFFSET  0x10
0137 #define IRQ_SIR_FIQ_REG_OFFSET  0x14
0138 #define IRQ_CONTROL_REG_OFFSET  0x18
0139 #define IRQ_ISR_REG_OFFSET  0x9c
0140 #define IRQ_ILR0_REG_OFFSET 0x1c
0141 #define IRQ_GMR_REG_OFFSET  0xa0
0142
0143 #endif
0144
0145 /* Timer32K for 1610 and 1710*/
0146 #define OMAP_TIMER32K_BASE  0xFFFBC400
0147
0148 /*
0149  * ---------------------------------------------------------------------------
0150  * TIPB bus interface
0151  * ---------------------------------------------------------------------------
0152  */
0153 #define TIPB_PUBLIC_CNTL_BASE       0xfffed300
0154 #define MPU_PUBLIC_TIPB_CNTL        (TIPB_PUBLIC_CNTL_BASE + 0x8)
0155 #define TIPB_PRIVATE_CNTL_BASE      0xfffeca00
0156 #define MPU_PRIVATE_TIPB_CNTL       (TIPB_PRIVATE_CNTL_BASE + 0x8)
0157
0158 /*
0159  * ----------------------------------------------------------------------------
0160  * MPUI interface
0161  * ----------------------------------------------------------------------------
0162  */
0163 #define MPUI_BASE           (0xfffec900)
0164 #define MPUI_CTRL           (MPUI_BASE + 0x0)
0165 #define MPUI_DEBUG_ADDR         (MPUI_BASE + 0x4)
0166 #define MPUI_DEBUG_DATA         (MPUI_BASE + 0x8)
0167 #define MPUI_DEBUG_FLAG         (MPUI_BASE + 0xc)
0168 #define MPUI_STATUS_REG         (MPUI_BASE + 0x10)
0169 #define MPUI_DSP_STATUS         (MPUI_BASE + 0x14)
0170 #define MPUI_DSP_BOOT_CONFIG        (MPUI_BASE + 0x18)
0171 #define MPUI_DSP_API_CONFIG     (MPUI_BASE + 0x1c)
0172
0173 /*
0174  * ----------------------------------------------------------------------------
0175  * LED Pulse Generator
0176  * ----------------------------------------------------------------------------
0177  */
0178 #define OMAP_LPG1_BASE          0xfffbd000
0179 #define OMAP_LPG2_BASE          0xfffbd800
0180 #define OMAP_LPG1_LCR           (OMAP_LPG1_BASE + 0x00)
0181 #define OMAP_LPG1_PMR           (OMAP_LPG1_BASE + 0x04)
0182 #define OMAP_LPG2_LCR           (OMAP_LPG2_BASE + 0x00)
0183 #define OMAP_LPG2_PMR           (OMAP_LPG2_BASE + 0x04)
0184
0185 /*
0186  * ---------------------------------------------------------------------------
0187  * Processor specific defines
0188  * ---------------------------------------------------------------------------
0189  */
0190
0191 #include "omap7xx.h"
0192 #include "omap1510.h"
0193 #include "omap16xx.h"
0194
0195 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */