arm/mach-omap1/clock.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  linux/arch/arm/mach-omap1/clock.h
0004  *
0005  *  Copyright (C) 2004 - 2005, 2009 Nokia corporation
0006  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
0007  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
0008  */
0009
0010 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
0011 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
0012
0013 #include <linux/clk.h>
0014 #include <linux/clkdev.h>
0015 #include <linux/clk-provider.h>
0016
0017 struct module;
0018 struct omap1_clk;
0019
0020 struct omap_clk {
0021     u16             cpu;
0022     struct clk_lookup       lk;
0023 };
0024
0025 #define CLK(dev, con, ck, cp)       \
0026     {               \
0027          .cpu = cp,     \
0028         .lk = {         \
0029             .dev_id = dev,  \
0030             .con_id = con,  \
0031             .clk_hw = ck,   \
0032         },          \
0033     }
0034
0035 /* Platform flags for the clkdev-OMAP integration code */
0036 #define CK_310      (1 << 0)
0037 #define CK_7XX      (1 << 1)    /* 7xx, 850 */
0038 #define CK_1510     (1 << 2)
0039 #define CK_16XX     (1 << 3)    /* 16xx, 17xx, 5912 */
0040 #define CK_1710     (1 << 4)    /* 1710 extra for rate selection */
0041
0042 /**
0043  * struct clkops - some clock function pointers
0044  * @enable: fn ptr that enables the current clock in hardware
0045  * @disable: fn ptr that enables the current clock in hardware
0046  * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
0047  */
0048 struct clkops {
0049     int         (*enable)(struct omap1_clk *clk);
0050     void            (*disable)(struct omap1_clk *clk);
0051 };
0052
0053 /*
0054  * struct clk.flags possibilities
0055  *
0056  * XXX document the rest of the clock flags here
0057  */
0058 #define ENABLE_REG_32BIT    (1 << 0)    /* Use 32-bit access */
0059 #define CLOCK_IDLE_CONTROL  (1 << 1)
0060 #define CLOCK_NO_IDLE_PARENT    (1 << 2)
0061
0062 /**
0063  * struct omap1_clk - OMAP1 struct clk
0064  * @hw: struct clk_hw for common clock framework integration
0065  * @ops: struct clkops * for this clock
0066  * @rate: current clock rate
0067  * @enable_reg: register to write to enable the clock (see @enable_bit)
0068  * @recalc: fn ptr that returns the clock's current rate
0069  * @set_rate: fn ptr that can change the clock's current rate
0070  * @round_rate: fn ptr that can round the clock's current rate
0071  * @init: fn ptr to do clock-specific initialization
0072  * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
0073  * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
0074  * @flags: see "struct clk.flags possibilities" above
0075  * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
0076  */
0077 struct omap1_clk {
0078     struct clk_hw       hw;
0079     const struct clkops *ops;
0080     unsigned long       rate;
0081     void __iomem        *enable_reg;
0082     unsigned long       (*recalc)(struct omap1_clk *clk, unsigned long rate);
0083     int         (*set_rate)(struct omap1_clk *clk, unsigned long rate,
0084                         unsigned long p_rate);
0085     long            (*round_rate)(struct omap1_clk *clk, unsigned long rate,
0086                           unsigned long *p_rate);
0087     int         (*init)(struct omap1_clk *clk);
0088     u8          enable_bit;
0089     u8          fixed_div;
0090     u8          flags;
0091     u8          rate_offset;
0092 };
0093 #define to_omap1_clk(_hw)   container_of(_hw, struct omap1_clk, hw)
0094
0095 void propagate_rate(struct omap1_clk *clk);
0096 unsigned long followparent_recalc(struct omap1_clk *clk, unsigned long p_rate);
0097 unsigned long omap_fixed_divisor_recalc(struct omap1_clk *clk, unsigned long p_rate);
0098
0099 extern struct omap1_clk dummy_ck;
0100
0101 int omap1_clk_init(void);
0102 void omap1_clk_late_init(void);
0103 unsigned long omap1_ckctl_recalc(struct omap1_clk *clk, unsigned long p_rate);
0104 long omap1_round_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
0105 int omap1_set_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
0106 unsigned long omap1_sossi_recalc(struct omap1_clk *clk, unsigned long p_rate);
0107 unsigned long omap1_ckctl_recalc_dsp_domain(struct omap1_clk *clk, unsigned long p_rate);
0108 int omap1_clk_set_rate_dsp_domain(struct omap1_clk *clk, unsigned long rate,
0109                   unsigned long p_rate);
0110 long omap1_round_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
0111 int omap1_set_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
0112 unsigned long omap1_uart_recalc(struct omap1_clk *clk, unsigned long p_rate);
0113 int omap1_set_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
0114 long omap1_round_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
0115 int omap1_init_ext_clk(struct omap1_clk *clk);
0116 int omap1_select_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
0117 long omap1_round_to_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
0118 int omap1_clk_set_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
0119 long omap1_clk_round_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate,
0120                     unsigned long *p_rate);
0121
0122 struct uart_clk {
0123     struct omap1_clk    clk;
0124     unsigned long       sysc_addr;
0125 };
0126
0127 /* Provide a method for preventing idling some ARM IDLECT clocks */
0128 struct arm_idlect1_clk {
0129     struct omap1_clk    clk;
0130     unsigned long       no_idle_count;
0131     __u8            idlect_shift;
0132 };
0133
0134 /* ARM_CKCTL bit shifts */
0135 #define CKCTL_PERDIV_OFFSET 0
0136 #define CKCTL_LCDDIV_OFFSET 2
0137 #define CKCTL_ARMDIV_OFFSET 4
0138 #define CKCTL_DSPDIV_OFFSET 6
0139 #define CKCTL_TCDIV_OFFSET  8
0140 #define CKCTL_DSPMMUDIV_OFFSET  10
0141 /*#define ARM_TIMXO     12*/
0142 #define EN_DSPCK        13
0143 /*#define ARM_INTHCK_SEL    14*/ /* Divide-by-2 for mpu inth_ck */
0144 /* DSP_CKCTL bit shifts */
0145 #define CKCTL_DSPPERDIV_OFFSET  0
0146
0147 /* ARM_IDLECT2 bit shifts */
0148 #define EN_WDTCK    0
0149 #define EN_XORPCK   1
0150 #define EN_PERCK    2
0151 #define EN_LCDCK    3
0152 #define EN_LBCK     4 /* Not on 1610/1710 */
0153 /*#define EN_HSABCK 5*/
0154 #define EN_APICK    6
0155 #define EN_TIMCK    7
0156 #define DMACK_REQ   8
0157 #define EN_GPIOCK   9 /* Not on 1610/1710 */
0158 /*#define EN_LBFREECK   10*/
0159 #define EN_CKOUT_ARM    11
0160
0161 /* ARM_IDLECT3 bit shifts */
0162 #define EN_OCPI_CK  0
0163 #define EN_TC1_CK   2
0164 #define EN_TC2_CK   4
0165
0166 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
0167 #define EN_DSPTIMCK 5
0168
0169 /* Various register defines for clock controls scattered around OMAP chip */
0170 #define SDW_MCLK_INV_BIT    2   /* In ULPD_CLKC_CTRL */
0171 #define USB_MCLK_EN_BIT     4   /* In ULPD_CLKC_CTRL */
0172 #define USB_HOST_HHC_UHOST_EN   9   /* In MOD_CONF_CTRL_0 */
0173 #define SWD_ULPD_PLL_CLK_REQ    1   /* In SWD_CLK_DIV_CTRL_SEL */
0174 #define COM_ULPD_PLL_CLK_REQ    1   /* In COM_CLK_DIV_CTRL_SEL */
0175 #define SWD_CLK_DIV_CTRL_SEL    0xfffe0874
0176 #define COM_CLK_DIV_CTRL_SEL    0xfffe0878
0177 #define SOFT_REQ_REG        0xfffe0834
0178 #define SOFT_REQ_REG2       0xfffe0880
0179
0180 extern __u32 arm_idlect1_mask;
0181 extern struct omap1_clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
0182
0183 extern const struct clkops clkops_dspck;
0184 extern const struct clkops clkops_uart_16xx;
0185 extern const struct clkops clkops_generic;
0186
0187 /* used for passing SoC type to omap1_{select,round_to}_table_rate() */
0188 extern u32 cpu_mask;
0189
0190 extern const struct clk_ops omap1_clk_null_ops;
0191 extern const struct clk_ops omap1_clk_gate_ops;
0192 extern const struct clk_ops omap1_clk_rate_ops;
0193 extern const struct clk_ops omap1_clk_full_ops;
0194
0195 #endif