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0005 #define pr_fmt(fmt) "nuvoton,npcm7xx-smp: " fmt
0006
0007 #include <linux/delay.h>
0008 #include <linux/device.h>
0009 #include <linux/smp.h>
0010 #include <linux/io.h>
0011 #include <linux/of.h>
0012 #include <linux/of_device.h>
0013 #include <linux/of_platform.h>
0014 #include <linux/of_address.h>
0015 #include <asm/cacheflush.h>
0016 #include <asm/smp.h>
0017 #include <asm/smp_plat.h>
0018 #include <asm/smp_scu.h>
0019
0020 #define NPCM7XX_SCRPAD_REG 0x13c
0021
0022 extern void npcm7xx_secondary_startup(void);
0023
0024 static int npcm7xx_smp_boot_secondary(unsigned int cpu,
0025 struct task_struct *idle)
0026 {
0027 struct device_node *gcr_np;
0028 void __iomem *gcr_base;
0029 int ret = 0;
0030
0031 gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr");
0032 if (!gcr_np) {
0033 pr_err("no gcr device node\n");
0034 ret = -ENODEV;
0035 goto out;
0036 }
0037 gcr_base = of_iomap(gcr_np, 0);
0038 if (!gcr_base) {
0039 pr_err("could not iomap gcr");
0040 ret = -ENOMEM;
0041 goto out;
0042 }
0043
0044
0045 iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +
0046 NPCM7XX_SCRPAD_REG);
0047
0048 dsb_sev();
0049
0050 iounmap(gcr_base);
0051 out:
0052 return ret;
0053 }
0054
0055 static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)
0056 {
0057 struct device_node *scu_np;
0058 void __iomem *scu_base;
0059
0060 scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
0061 if (!scu_np) {
0062 pr_err("no scu device node\n");
0063 return;
0064 }
0065 scu_base = of_iomap(scu_np, 0);
0066 if (!scu_base) {
0067 pr_err("could not iomap scu");
0068 return;
0069 }
0070
0071 scu_enable(scu_base);
0072
0073 iounmap(scu_base);
0074 }
0075
0076 static struct smp_operations npcm7xx_smp_ops __initdata = {
0077 .smp_prepare_cpus = npcm7xx_smp_prepare_cpus,
0078 .smp_boot_secondary = npcm7xx_smp_boot_secondary,
0079 };
0080
0081 CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm750-smp", &npcm7xx_smp_ops);