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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Power Management Service Unit(PMSU) support for Armada 370/XP platforms.
0004  *
0005  * Copyright (C) 2012 Marvell
0006  *
0007  * Yehuda Yitschak <yehuday@marvell.com>
0008  * Gregory Clement <gregory.clement@free-electrons.com>
0009  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0010  *
0011  * The Armada 370 and Armada XP SOCs have a power management service
0012  * unit which is responsible for powering down and waking up CPUs and
0013  * other SOC units
0014  */
0015 
0016 #define pr_fmt(fmt) "mvebu-pmsu: " fmt
0017 
0018 #include <linux/clk.h>
0019 #include <linux/cpu_pm.h>
0020 #include <linux/delay.h>
0021 #include <linux/init.h>
0022 #include <linux/io.h>
0023 #include <linux/kernel.h>
0024 #include <linux/mbus.h>
0025 #include <linux/mvebu-pmsu.h>
0026 #include <linux/of_address.h>
0027 #include <linux/of_device.h>
0028 #include <linux/platform_device.h>
0029 #include <linux/resource.h>
0030 #include <linux/slab.h>
0031 #include <linux/smp.h>
0032 #include <asm/cacheflush.h>
0033 #include <asm/cp15.h>
0034 #include <asm/smp_scu.h>
0035 #include <asm/smp_plat.h>
0036 #include <asm/suspend.h>
0037 #include <asm/tlbflush.h>
0038 #include "common.h"
0039 #include "pmsu.h"
0040 
0041 #define PMSU_BASE_OFFSET    0x100
0042 #define PMSU_REG_SIZE       0x1000
0043 
0044 /* PMSU MP registers */
0045 #define PMSU_CONTROL_AND_CONFIG(cpu)        ((cpu * 0x100) + 0x104)
0046 #define PMSU_CONTROL_AND_CONFIG_DFS_REQ     BIT(18)
0047 #define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ   BIT(16)
0048 #define PMSU_CONTROL_AND_CONFIG_L2_PWDDN    BIT(20)
0049 
0050 #define PMSU_CPU_POWER_DOWN_CONTROL(cpu)    ((cpu * 0x100) + 0x108)
0051 
0052 #define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP  BIT(0)
0053 
0054 #define PMSU_STATUS_AND_MASK(cpu)       ((cpu * 0x100) + 0x10c)
0055 #define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT  BIT(16)
0056 #define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT   BIT(17)
0057 #define PMSU_STATUS_AND_MASK_IRQ_WAKEUP     BIT(20)
0058 #define PMSU_STATUS_AND_MASK_FIQ_WAKEUP     BIT(21)
0059 #define PMSU_STATUS_AND_MASK_DBG_WAKEUP     BIT(22)
0060 #define PMSU_STATUS_AND_MASK_IRQ_MASK       BIT(24)
0061 #define PMSU_STATUS_AND_MASK_FIQ_MASK       BIT(25)
0062 
0063 #define PMSU_EVENT_STATUS_AND_MASK(cpu)     ((cpu * 0x100) + 0x120)
0064 #define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE        BIT(1)
0065 #define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK   BIT(17)
0066 
0067 #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)
0068 
0069 /* PMSU fabric registers */
0070 #define L2C_NFABRIC_PM_CTL          0x4
0071 #define L2C_NFABRIC_PM_CTL_PWR_DOWN     BIT(20)
0072 
0073 /* PMSU delay registers */
0074 #define PMSU_POWERDOWN_DELAY            0xF04
0075 #define PMSU_POWERDOWN_DELAY_PMU        BIT(1)
0076 #define PMSU_POWERDOWN_DELAY_MASK       0xFFFE
0077 #define PMSU_DFLT_ARMADA38X_DELAY           0x64
0078 
0079 /* CA9 MPcore SoC Control registers */
0080 
0081 #define MPCORE_RESET_CTL            0x64
0082 #define MPCORE_RESET_CTL_L2         BIT(0)
0083 #define MPCORE_RESET_CTL_DEBUG          BIT(16)
0084 
0085 #define SRAM_PHYS_BASE  0xFFFF0000
0086 #define BOOTROM_BASE    0xFFF00000
0087 #define BOOTROM_SIZE    0x100000
0088 
0089 #define ARMADA_370_CRYPT0_ENG_TARGET   0x9
0090 #define ARMADA_370_CRYPT0_ENG_ATTR     0x1
0091 
0092 extern void ll_disable_coherency(void);
0093 extern void ll_enable_coherency(void);
0094 
0095 extern void armada_370_xp_cpu_resume(void);
0096 extern void armada_38x_cpu_resume(void);
0097 
0098 static phys_addr_t pmsu_mp_phys_base;
0099 static void __iomem *pmsu_mp_base;
0100 
0101 static void *mvebu_cpu_resume;
0102 
0103 static const struct of_device_id of_pmsu_table[] = {
0104     { .compatible = "marvell,armada-370-pmsu", },
0105     { .compatible = "marvell,armada-370-xp-pmsu", },
0106     { .compatible = "marvell,armada-380-pmsu", },
0107     { /* end of list */ },
0108 };
0109 
0110 void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
0111 {
0112     writel(__pa_symbol(boot_addr), pmsu_mp_base +
0113         PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
0114 }
0115 
0116 extern unsigned char mvebu_boot_wa_start[];
0117 extern unsigned char mvebu_boot_wa_end[];
0118 
0119 /*
0120  * This function sets up the boot address workaround needed for SMP
0121  * boot on Armada 375 Z1 and cpuidle on Armada 370. It unmaps the
0122  * BootROM Mbus window, and instead remaps a crypto SRAM into which a
0123  * custom piece of code is copied to replace the problematic BootROM.
0124  */
0125 int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
0126                  unsigned int crypto_eng_attribute,
0127                  phys_addr_t resume_addr_reg)
0128 {
0129     void __iomem *sram_virt_base;
0130     u32 code_len = mvebu_boot_wa_end - mvebu_boot_wa_start;
0131 
0132     mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
0133     mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute,
0134                     SRAM_PHYS_BASE, SZ_64K);
0135 
0136     sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
0137     if (!sram_virt_base) {
0138         pr_err("Unable to map SRAM to setup the boot address WA\n");
0139         return -ENOMEM;
0140     }
0141 
0142     memcpy(sram_virt_base, &mvebu_boot_wa_start, code_len);
0143 
0144     /*
0145      * The last word of the code copied in SRAM must contain the
0146      * physical base address of the PMSU register. We
0147      * intentionally store this address in the native endianness
0148      * of the system.
0149      */
0150     __raw_writel((unsigned long)resume_addr_reg,
0151              sram_virt_base + code_len - 4);
0152 
0153     iounmap(sram_virt_base);
0154 
0155     return 0;
0156 }
0157 
0158 static int __init mvebu_v7_pmsu_init(void)
0159 {
0160     struct device_node *np;
0161     struct resource res;
0162     int ret = 0;
0163 
0164     np = of_find_matching_node(NULL, of_pmsu_table);
0165     if (!np)
0166         return 0;
0167 
0168     pr_info("Initializing Power Management Service Unit\n");
0169 
0170     if (of_address_to_resource(np, 0, &res)) {
0171         pr_err("unable to get resource\n");
0172         ret = -ENOENT;
0173         goto out;
0174     }
0175 
0176     if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) {
0177         pr_warn(FW_WARN "deprecated pmsu binding\n");
0178         res.start = res.start - PMSU_BASE_OFFSET;
0179         res.end = res.start + PMSU_REG_SIZE - 1;
0180     }
0181 
0182     if (!request_mem_region(res.start, resource_size(&res),
0183                 np->full_name)) {
0184         pr_err("unable to request region\n");
0185         ret = -EBUSY;
0186         goto out;
0187     }
0188 
0189     pmsu_mp_phys_base = res.start;
0190 
0191     pmsu_mp_base = ioremap(res.start, resource_size(&res));
0192     if (!pmsu_mp_base) {
0193         pr_err("unable to map registers\n");
0194         release_mem_region(res.start, resource_size(&res));
0195         ret = -ENOMEM;
0196         goto out;
0197     }
0198 
0199  out:
0200     of_node_put(np);
0201     return ret;
0202 }
0203 
0204 static void mvebu_v7_pmsu_enable_l2_powerdown_onidle(void)
0205 {
0206     u32 reg;
0207 
0208     if (pmsu_mp_base == NULL)
0209         return;
0210 
0211     /* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */
0212     reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL);
0213     reg |= L2C_NFABRIC_PM_CTL_PWR_DOWN;
0214     writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
0215 }
0216 
0217 enum pmsu_idle_prepare_flags {
0218     PMSU_PREPARE_NORMAL = 0,
0219     PMSU_PREPARE_DEEP_IDLE = BIT(0),
0220     PMSU_PREPARE_SNOOP_DISABLE = BIT(1),
0221 };
0222 
0223 /* No locking is needed because we only access per-CPU registers */
0224 static int mvebu_v7_pmsu_idle_prepare(unsigned long flags)
0225 {
0226     unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
0227     u32 reg;
0228 
0229     if (pmsu_mp_base == NULL)
0230         return -EINVAL;
0231 
0232     /*
0233      * Adjust the PMSU configuration to wait for WFI signal, enable
0234      * IRQ and FIQ as wakeup events, set wait for snoop queue empty
0235      * indication and mask IRQ and FIQ from CPU
0236      */
0237     reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
0238     reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT    |
0239            PMSU_STATUS_AND_MASK_IRQ_WAKEUP       |
0240            PMSU_STATUS_AND_MASK_FIQ_WAKEUP       |
0241            PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT |
0242            PMSU_STATUS_AND_MASK_IRQ_MASK         |
0243            PMSU_STATUS_AND_MASK_FIQ_MASK;
0244     writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
0245 
0246     reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
0247     /* ask HW to power down the L2 Cache if needed */
0248     if (flags & PMSU_PREPARE_DEEP_IDLE)
0249         reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
0250 
0251     /* request power down */
0252     reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
0253     writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
0254 
0255     if (flags & PMSU_PREPARE_SNOOP_DISABLE) {
0256         /* Disable snoop disable by HW - SW is taking care of it */
0257         reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
0258         reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
0259         writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
0260     }
0261 
0262     return 0;
0263 }
0264 
0265 int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
0266 {
0267     unsigned long flags = PMSU_PREPARE_SNOOP_DISABLE;
0268     int ret;
0269 
0270     if (deepidle)
0271         flags |= PMSU_PREPARE_DEEP_IDLE;
0272 
0273     ret = mvebu_v7_pmsu_idle_prepare(flags);
0274     if (ret)
0275         return ret;
0276 
0277     v7_exit_coherency_flush(all);
0278 
0279     ll_disable_coherency();
0280 
0281     dsb();
0282 
0283     wfi();
0284 
0285     /* If we are here, wfi failed. As processors run out of
0286      * coherency for some time, tlbs might be stale, so flush them
0287      */
0288     local_flush_tlb_all();
0289 
0290     ll_enable_coherency();
0291 
0292     /* Test the CR_C bit and set it if it was cleared */
0293     asm volatile(
0294     "mrc    p15, 0, r0, c1, c0, 0 \n\t"
0295     "tst    r0, %0 \n\t"
0296     "orreq  r0, r0, #(1 << 2) \n\t"
0297     "mcreq  p15, 0, r0, c1, c0, 0 \n\t"
0298     "isb    "
0299     : : "Ir" (CR_C) : "r0");
0300 
0301     pr_debug("Failed to suspend the system\n");
0302 
0303     return 0;
0304 }
0305 
0306 static int armada_370_xp_cpu_suspend(unsigned long deepidle)
0307 {
0308     return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter);
0309 }
0310 
0311 int armada_38x_do_cpu_suspend(unsigned long deepidle)
0312 {
0313     unsigned long flags = 0;
0314 
0315     if (deepidle)
0316         flags |= PMSU_PREPARE_DEEP_IDLE;
0317 
0318     mvebu_v7_pmsu_idle_prepare(flags);
0319     /*
0320      * Already flushed cache, but do it again as the outer cache
0321      * functions dirty the cache with spinlocks
0322      */
0323     v7_exit_coherency_flush(louis);
0324 
0325     scu_power_mode(mvebu_get_scu_base(), SCU_PM_POWEROFF);
0326 
0327     cpu_do_idle();
0328 
0329     return 1;
0330 }
0331 
0332 static int armada_38x_cpu_suspend(unsigned long deepidle)
0333 {
0334     return cpu_suspend(false, armada_38x_do_cpu_suspend);
0335 }
0336 
0337 /* No locking is needed because we only access per-CPU registers */
0338 void mvebu_v7_pmsu_idle_exit(void)
0339 {
0340     unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
0341     u32 reg;
0342 
0343     if (pmsu_mp_base == NULL)
0344         return;
0345     /* cancel ask HW to power down the L2 Cache if possible */
0346     reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
0347     reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
0348     writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
0349 
0350     /* cancel Enable wakeup events and mask interrupts */
0351     reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
0352     reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP | PMSU_STATUS_AND_MASK_FIQ_WAKEUP);
0353     reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
0354     reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT;
0355     reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK | PMSU_STATUS_AND_MASK_FIQ_MASK);
0356     writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
0357 }
0358 
0359 static int mvebu_v7_cpu_pm_notify(struct notifier_block *self,
0360                     unsigned long action, void *hcpu)
0361 {
0362     if (action == CPU_PM_ENTER) {
0363         unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
0364         mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cpu_resume);
0365     } else if (action == CPU_PM_EXIT) {
0366         mvebu_v7_pmsu_idle_exit();
0367     }
0368 
0369     return NOTIFY_OK;
0370 }
0371 
0372 static struct notifier_block mvebu_v7_cpu_pm_notifier = {
0373     .notifier_call = mvebu_v7_cpu_pm_notify,
0374 };
0375 
0376 static struct platform_device mvebu_v7_cpuidle_device;
0377 
0378 static int broken_idle(struct device_node *np)
0379 {
0380     if (of_property_read_bool(np, "broken-idle")) {
0381         pr_warn("CPU idle is currently broken: disabling\n");
0382         return 1;
0383     }
0384 
0385     return 0;
0386 }
0387 
0388 static __init int armada_370_cpuidle_init(void)
0389 {
0390     struct device_node *np;
0391     phys_addr_t redirect_reg;
0392 
0393     np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
0394     if (!np)
0395         return -ENODEV;
0396 
0397     if (broken_idle(np))
0398         goto end;
0399 
0400     /*
0401      * On Armada 370, there is "a slow exit process from the deep
0402      * idle state due to heavy L1/L2 cache cleanup operations
0403      * performed by the BootROM software". To avoid this, we
0404      * replace the restart code of the bootrom by a a simple jump
0405      * to the boot address. Then the code located at this boot
0406      * address will take care of the initialization.
0407      */
0408     redirect_reg = pmsu_mp_phys_base + PMSU_BOOT_ADDR_REDIRECT_OFFSET(0);
0409     mvebu_setup_boot_addr_wa(ARMADA_370_CRYPT0_ENG_TARGET,
0410                  ARMADA_370_CRYPT0_ENG_ATTR,
0411                  redirect_reg);
0412 
0413     mvebu_cpu_resume = armada_370_xp_cpu_resume;
0414     mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
0415     mvebu_v7_cpuidle_device.name = "cpuidle-armada-370";
0416 
0417 end:
0418     of_node_put(np);
0419     return 0;
0420 }
0421 
0422 static __init int armada_38x_cpuidle_init(void)
0423 {
0424     struct device_node *np;
0425     void __iomem *mpsoc_base;
0426     u32 reg;
0427 
0428     pr_warn("CPU idle is currently broken on Armada 38x: disabling\n");
0429     return 0;
0430 
0431     np = of_find_compatible_node(NULL, NULL,
0432                      "marvell,armada-380-coherency-fabric");
0433     if (!np)
0434         return -ENODEV;
0435 
0436     if (broken_idle(np))
0437         goto end;
0438 
0439     of_node_put(np);
0440 
0441     np = of_find_compatible_node(NULL, NULL,
0442                      "marvell,armada-380-mpcore-soc-ctrl");
0443     if (!np)
0444         return -ENODEV;
0445     mpsoc_base = of_iomap(np, 0);
0446     BUG_ON(!mpsoc_base);
0447 
0448     /* Set up reset mask when powering down the cpus */
0449     reg = readl(mpsoc_base + MPCORE_RESET_CTL);
0450     reg |= MPCORE_RESET_CTL_L2;
0451     reg |= MPCORE_RESET_CTL_DEBUG;
0452     writel(reg, mpsoc_base + MPCORE_RESET_CTL);
0453     iounmap(mpsoc_base);
0454 
0455     /* Set up delay */
0456     reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY);
0457     reg &= ~PMSU_POWERDOWN_DELAY_MASK;
0458     reg |= PMSU_DFLT_ARMADA38X_DELAY;
0459     reg |= PMSU_POWERDOWN_DELAY_PMU;
0460     writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY);
0461 
0462     mvebu_cpu_resume = armada_38x_cpu_resume;
0463     mvebu_v7_cpuidle_device.dev.platform_data = armada_38x_cpu_suspend;
0464     mvebu_v7_cpuidle_device.name = "cpuidle-armada-38x";
0465 
0466 end:
0467     of_node_put(np);
0468     return 0;
0469 }
0470 
0471 static __init int armada_xp_cpuidle_init(void)
0472 {
0473     struct device_node *np;
0474 
0475     np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
0476     if (!np)
0477         return -ENODEV;
0478 
0479     if (broken_idle(np))
0480         goto end;
0481 
0482     mvebu_cpu_resume = armada_370_xp_cpu_resume;
0483     mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
0484     mvebu_v7_cpuidle_device.name = "cpuidle-armada-xp";
0485 
0486 end:
0487     of_node_put(np);
0488     return 0;
0489 }
0490 
0491 static int __init mvebu_v7_cpu_pm_init(void)
0492 {
0493     struct device_node *np;
0494     int ret;
0495 
0496     np = of_find_matching_node(NULL, of_pmsu_table);
0497     if (!np)
0498         return 0;
0499     of_node_put(np);
0500 
0501     /*
0502      * Currently the CPU idle support for Armada 38x is broken, as
0503      * the CPU hotplug uses some of the CPU idle functions it is
0504      * broken too, so let's disable it
0505      */
0506     if (of_machine_is_compatible("marvell,armada380")) {
0507         cpu_hotplug_disable();
0508         pr_warn("CPU hotplug support is currently broken on Armada 38x: disabling\n");
0509     }
0510 
0511     if (of_machine_is_compatible("marvell,armadaxp"))
0512         ret = armada_xp_cpuidle_init();
0513     else if (of_machine_is_compatible("marvell,armada370"))
0514         ret = armada_370_cpuidle_init();
0515     else if (of_machine_is_compatible("marvell,armada380"))
0516         ret = armada_38x_cpuidle_init();
0517     else
0518         return 0;
0519 
0520     if (ret)
0521         return ret;
0522 
0523     mvebu_v7_pmsu_enable_l2_powerdown_onidle();
0524     if (mvebu_v7_cpuidle_device.name)
0525         platform_device_register(&mvebu_v7_cpuidle_device);
0526     cpu_pm_register_notifier(&mvebu_v7_cpu_pm_notifier);
0527 
0528     return 0;
0529 }
0530 
0531 arch_initcall(mvebu_v7_cpu_pm_init);
0532 early_initcall(mvebu_v7_pmsu_init);
0533 
0534 static void mvebu_pmsu_dfs_request_local(void *data)
0535 {
0536     u32 reg;
0537     u32 cpu = smp_processor_id();
0538     unsigned long flags;
0539 
0540     local_irq_save(flags);
0541 
0542     /* Prepare to enter idle */
0543     reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
0544     reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT |
0545            PMSU_STATUS_AND_MASK_IRQ_MASK     |
0546            PMSU_STATUS_AND_MASK_FIQ_MASK;
0547     writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
0548 
0549     /* Request the DFS transition */
0550     reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
0551     reg |= PMSU_CONTROL_AND_CONFIG_DFS_REQ;
0552     writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
0553 
0554     /* The fact of entering idle will trigger the DFS transition */
0555     wfi();
0556 
0557     /*
0558      * We're back from idle, the DFS transition has completed,
0559      * clear the idle wait indication.
0560      */
0561     reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
0562     reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
0563     writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
0564 
0565     local_irq_restore(flags);
0566 }
0567 
0568 int mvebu_pmsu_dfs_request(int cpu)
0569 {
0570     unsigned long timeout;
0571     int hwcpu = cpu_logical_map(cpu);
0572     u32 reg;
0573 
0574     /* Clear any previous DFS DONE event */
0575     reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
0576     reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE;
0577     writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
0578 
0579     /* Mask the DFS done interrupt, since we are going to poll */
0580     reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
0581     reg |= PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
0582     writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
0583 
0584     /* Trigger the DFS on the appropriate CPU */
0585     smp_call_function_single(cpu, mvebu_pmsu_dfs_request_local,
0586                  NULL, false);
0587 
0588     /* Poll until the DFS done event is generated */
0589     timeout = jiffies + HZ;
0590     while (time_before(jiffies, timeout)) {
0591         reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
0592         if (reg & PMSU_EVENT_STATUS_AND_MASK_DFS_DONE)
0593             break;
0594         udelay(10);
0595     }
0596 
0597     if (time_after(jiffies, timeout))
0598         return -ETIME;
0599 
0600     /* Restore the DFS mask to its original state */
0601     reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
0602     reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
0603     writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
0604 
0605     return 0;
0606 }
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