arm/mach-mvebu/pm.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Suspend/resume support. Currently supporting Armada XP only.
0004  *
0005  * Copyright (C) 2014 Marvell
0006  *
0007  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0008  */
0009
0010 #include <linux/cpu_pm.h>
0011 #include <linux/delay.h>
0012 #include <linux/gpio.h>
0013 #include <linux/io.h>
0014 #include <linux/kernel.h>
0015 #include <linux/mbus.h>
0016 #include <linux/of_address.h>
0017 #include <linux/suspend.h>
0018 #include <asm/cacheflush.h>
0019 #include <asm/outercache.h>
0020 #include <asm/suspend.h>
0021
0022 #include "coherency.h"
0023 #include "common.h"
0024 #include "pmsu.h"
0025
0026 #define SDRAM_CONFIG_OFFS                  0x0
0027 #define  SDRAM_CONFIG_SR_MODE_BIT          BIT(24)
0028 #define SDRAM_OPERATION_OFFS               0x18
0029 #define  SDRAM_OPERATION_SELF_REFRESH      0x7
0030 #define SDRAM_DLB_EVICTION_OFFS            0x30c
0031 #define  SDRAM_DLB_EVICTION_THRESHOLD_MASK 0xff
0032
0033 static void (*mvebu_board_pm_enter)(void __iomem *sdram_reg, u32 srcmd);
0034 static void __iomem *sdram_ctrl;
0035
0036 static int mvebu_pm_powerdown(unsigned long data)
0037 {
0038     u32 reg, srcmd;
0039
0040     flush_cache_all();
0041     outer_flush_all();
0042
0043     /*
0044      * Issue a Data Synchronization Barrier instruction to ensure
0045      * that all state saving has been completed.
0046      */
0047     dsb();
0048
0049     /* Flush the DLB and wait ~7 usec */
0050     reg = readl(sdram_ctrl + SDRAM_DLB_EVICTION_OFFS);
0051     reg &= ~SDRAM_DLB_EVICTION_THRESHOLD_MASK;
0052     writel(reg, sdram_ctrl + SDRAM_DLB_EVICTION_OFFS);
0053
0054     udelay(7);
0055
0056     /* Set DRAM in battery backup mode */
0057     reg = readl(sdram_ctrl + SDRAM_CONFIG_OFFS);
0058     reg &= ~SDRAM_CONFIG_SR_MODE_BIT;
0059     writel(reg, sdram_ctrl + SDRAM_CONFIG_OFFS);
0060
0061     /* Prepare to go to self-refresh */
0062
0063     srcmd = readl(sdram_ctrl + SDRAM_OPERATION_OFFS);
0064     srcmd &= ~0x1F;
0065     srcmd |= SDRAM_OPERATION_SELF_REFRESH;
0066
0067     mvebu_board_pm_enter(sdram_ctrl + SDRAM_OPERATION_OFFS, srcmd);
0068
0069     return 0;
0070 }
0071
0072 #define BOOT_INFO_ADDR      0x3000
0073 #define BOOT_MAGIC_WORD     0xdeadb002
0074 #define BOOT_MAGIC_LIST_END 0xffffffff
0075
0076 /*
0077  * Those registers are accessed before switching the internal register
0078  * base, which is why we hardcode the 0xd0000000 base address, the one
0079  * used by the SoC out of reset.
0080  */
0081 #define MBUS_WINDOW_12_CTRL       0xd00200b0
0082 #define MBUS_INTERNAL_REG_ADDRESS 0xd0020080
0083
0084 #define SDRAM_WIN_BASE_REG(x)   (0x20180 + (0x8*x))
0085 #define SDRAM_WIN_CTRL_REG(x)   (0x20184 + (0x8*x))
0086
0087 static phys_addr_t mvebu_internal_reg_base(void)
0088 {
0089     struct device_node *np;
0090     __be32 in_addr[2];
0091
0092     np = of_find_node_by_name(NULL, "internal-regs");
0093     BUG_ON(!np);
0094
0095     /*
0096      * Ask the DT what is the internal register address on this
0097      * platform. In the mvebu-mbus DT binding, 0xf0010000
0098      * corresponds to the internal register window.
0099      */
0100     in_addr[0] = cpu_to_be32(0xf0010000);
0101     in_addr[1] = 0x0;
0102
0103     return of_translate_address(np, in_addr);
0104 }
0105
0106 static void mvebu_pm_store_armadaxp_bootinfo(u32 *store_addr)
0107 {
0108     phys_addr_t resume_pc;
0109
0110     resume_pc = __pa_symbol(armada_370_xp_cpu_resume);
0111
0112     /*
0113      * The bootloader expects the first two words to be a magic
0114      * value (BOOT_MAGIC_WORD), followed by the address of the
0115      * resume code to jump to. Then, it expects a sequence of
0116      * (address, value) pairs, which can be used to restore the
0117      * value of certain registers. This sequence must end with the
0118      * BOOT_MAGIC_LIST_END magic value.
0119      */
0120
0121     writel(BOOT_MAGIC_WORD, store_addr++);
0122     writel(resume_pc, store_addr++);
0123
0124     /*
0125      * Some platforms remap their internal register base address
0126      * to 0xf1000000. However, out of reset, window 12 starts at
0127      * 0xf0000000 and ends at 0xf7ffffff, which would overlap with
0128      * the internal registers. Therefore, disable window 12.
0129      */
0130     writel(MBUS_WINDOW_12_CTRL, store_addr++);
0131     writel(0x0, store_addr++);
0132
0133     /*
0134      * Set the internal register base address to the value
0135      * expected by Linux, as read from the Device Tree.
0136      */
0137     writel(MBUS_INTERNAL_REG_ADDRESS, store_addr++);
0138     writel(mvebu_internal_reg_base(), store_addr++);
0139
0140     /*
0141      * Ask the mvebu-mbus driver to store the SDRAM window
0142      * configuration, which has to be restored by the bootloader
0143      * before re-entering the kernel on resume.
0144      */
0145     store_addr += mvebu_mbus_save_cpu_target(store_addr);
0146
0147     writel(BOOT_MAGIC_LIST_END, store_addr);
0148 }
0149
0150 static int mvebu_pm_store_bootinfo(void)
0151 {
0152     u32 *store_addr;
0153
0154     store_addr = phys_to_virt(BOOT_INFO_ADDR);
0155
0156     if (of_machine_is_compatible("marvell,armadaxp"))
0157         mvebu_pm_store_armadaxp_bootinfo(store_addr);
0158     else
0159         return -ENODEV;
0160
0161     return 0;
0162 }
0163
0164 static int mvebu_enter_suspend(void)
0165 {
0166     int ret;
0167
0168     ret = mvebu_pm_store_bootinfo();
0169     if (ret)
0170         return ret;
0171
0172     cpu_pm_enter();
0173
0174     cpu_suspend(0, mvebu_pm_powerdown);
0175
0176     outer_resume();
0177
0178     mvebu_v7_pmsu_idle_exit();
0179
0180     set_cpu_coherent();
0181
0182     cpu_pm_exit();
0183     return 0;
0184 }
0185
0186 static int mvebu_pm_enter(suspend_state_t state)
0187 {
0188     switch (state) {
0189     case PM_SUSPEND_STANDBY:
0190         cpu_do_idle();
0191         break;
0192     case PM_SUSPEND_MEM:
0193         pr_warn("Entering suspend to RAM. Only special wake-up sources will resume the system\n");
0194         return mvebu_enter_suspend();
0195     default:
0196         return -EINVAL;
0197     }
0198     return 0;
0199 }
0200
0201 static int mvebu_pm_valid(suspend_state_t state)
0202 {
0203     if (state == PM_SUSPEND_STANDBY)
0204         return 1;
0205
0206     if (state == PM_SUSPEND_MEM && mvebu_board_pm_enter != NULL)
0207         return 1;
0208
0209     return 0;
0210 }
0211
0212 static const struct platform_suspend_ops mvebu_pm_ops = {
0213     .enter = mvebu_pm_enter,
0214     .valid = mvebu_pm_valid,
0215 };
0216
0217 static int __init mvebu_pm_init(void)
0218 {
0219     if (!of_machine_is_compatible("marvell,armadaxp") &&
0220         !of_machine_is_compatible("marvell,armada370") &&
0221         !of_machine_is_compatible("marvell,armada380") &&
0222         !of_machine_is_compatible("marvell,armada390"))
0223         return -ENODEV;
0224
0225     suspend_set_ops(&mvebu_pm_ops);
0226
0227     return 0;
0228 }
0229
0230
0231 late_initcall(mvebu_pm_init);
0232
0233 int __init mvebu_pm_suspend_init(void (*board_pm_enter)(void __iomem *sdram_reg,
0234                             u32 srcmd))
0235 {
0236     struct device_node *np;
0237     struct resource res;
0238
0239     np = of_find_compatible_node(NULL, NULL,
0240                      "marvell,armada-xp-sdram-controller");
0241     if (!np)
0242         return -ENODEV;
0243
0244     if (of_address_to_resource(np, 0, &res)) {
0245         of_node_put(np);
0246         return -ENODEV;
0247     }
0248
0249     if (!request_mem_region(res.start, resource_size(&res),
0250                 np->full_name)) {
0251         of_node_put(np);
0252         return -EBUSY;
0253     }
0254
0255     sdram_ctrl = ioremap(res.start, resource_size(&res));
0256     if (!sdram_ctrl) {
0257         release_mem_region(res.start, resource_size(&res));
0258         of_node_put(np);
0259         return -ENOMEM;
0260     }
0261
0262     of_node_put(np);
0263
0264     mvebu_board_pm_enter = board_pm_enter;
0265
0266     return 0;
0267 }