arm/mach-mvebu/platsmp.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Symmetric Multi Processing (SMP) support for Armada XP
0004  *
0005  * Copyright (C) 2012 Marvell
0006  *
0007  * Lior Amsalem <alior@marvell.com>
0008  * Yehuda Yitschak <yehuday@marvell.com>
0009  * Gregory CLEMENT <gregory.clement@free-electrons.com>
0010  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0011  *
0012  * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
0013  * This file implements the routines for preparing the SMP infrastructure
0014  * and waking up the secondary CPUs
0015  */
0016
0017 #include <linux/init.h>
0018 #include <linux/smp.h>
0019 #include <linux/clk.h>
0020 #include <linux/of.h>
0021 #include <linux/of_address.h>
0022 #include <linux/mbus.h>
0023 #include <asm/cacheflush.h>
0024 #include <asm/smp_plat.h>
0025 #include "common.h"
0026 #include "armada-370-xp.h"
0027 #include "pmsu.h"
0028 #include "coherency.h"
0029
0030 #define ARMADA_XP_MAX_CPUS 4
0031
0032 #define AXP_BOOTROM_BASE 0xfff00000
0033 #define AXP_BOOTROM_SIZE 0x100000
0034
0035 static struct clk *boot_cpu_clk;
0036
0037 static struct clk *get_cpu_clk(int cpu)
0038 {
0039     struct clk *cpu_clk;
0040     struct device_node *np = of_get_cpu_node(cpu, NULL);
0041
0042     if (WARN(!np, "missing cpu node\n"))
0043         return NULL;
0044     cpu_clk = of_clk_get(np, 0);
0045     if (WARN_ON(IS_ERR(cpu_clk)))
0046         return NULL;
0047     return cpu_clk;
0048 }
0049
0050 static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
0051 {
0052     int ret, hw_cpu;
0053
0054     pr_info("Booting CPU %d\n", cpu);
0055
0056     hw_cpu = cpu_logical_map(cpu);
0057     mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup);
0058
0059     /*
0060      * This is needed to wake up CPUs in the offline state after
0061      * using CPU hotplug.
0062      */
0063     arch_send_wakeup_ipi_mask(cpumask_of(cpu));
0064
0065     /*
0066      * This is needed to take secondary CPUs out of reset on the
0067      * initial boot.
0068      */
0069     ret = mvebu_cpu_reset_deassert(hw_cpu);
0070     if (ret) {
0071         pr_warn("unable to boot CPU: %d\n", ret);
0072         return ret;
0073     }
0074
0075     return 0;
0076 }
0077
0078 /*
0079  * When a CPU is brought back online, either through CPU hotplug, or
0080  * because of the boot of a kexec'ed kernel, the PMSU configuration
0081  * for this CPU might be in the deep idle state, preventing this CPU
0082  * from receiving interrupts. Here, we therefore take out the current
0083  * CPU from this state, which was entered by armada_xp_cpu_die()
0084  * below.
0085  */
0086 static void armada_xp_secondary_init(unsigned int cpu)
0087 {
0088     mvebu_v7_pmsu_idle_exit();
0089 }
0090
0091 static void __init armada_xp_smp_init_cpus(void)
0092 {
0093     unsigned int ncores = num_possible_cpus();
0094
0095     if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
0096         panic("Invalid number of CPUs in DT\n");
0097 }
0098
0099 static int armada_xp_sync_secondary_clk(unsigned int cpu)
0100 {
0101     struct clk *cpu_clk = get_cpu_clk(cpu);
0102
0103     if (!cpu_clk || !boot_cpu_clk)
0104         return 0;
0105
0106     clk_prepare_enable(cpu_clk);
0107     clk_set_rate(cpu_clk, clk_get_rate(boot_cpu_clk));
0108
0109     return 0;
0110 }
0111
0112 static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
0113 {
0114     struct device_node *node;
0115     struct resource res;
0116     int err;
0117
0118     flush_cache_all();
0119     set_cpu_coherent();
0120
0121     boot_cpu_clk = get_cpu_clk(smp_processor_id());
0122     if (boot_cpu_clk) {
0123         clk_prepare_enable(boot_cpu_clk);
0124         cpuhp_setup_state_nocalls(CPUHP_AP_ARM_MVEBU_SYNC_CLOCKS,
0125                       "arm/mvebu/sync_clocks:online",
0126                       armada_xp_sync_secondary_clk, NULL);
0127     }
0128
0129     /*
0130      * In order to boot the secondary CPUs we need to ensure
0131      * the bootROM is mapped at the correct address.
0132      */
0133     node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
0134     if (!node)
0135         panic("Cannot find 'marvell,bootrom' compatible node");
0136
0137     err = of_address_to_resource(node, 0, &res);
0138     of_node_put(node);
0139     if (err < 0)
0140         panic("Cannot get 'bootrom' node address");
0141
0142     if (res.start != AXP_BOOTROM_BASE ||
0143         resource_size(&res) != AXP_BOOTROM_SIZE)
0144         panic("The address for the BootROM is incorrect");
0145 }
0146
0147 #ifdef CONFIG_HOTPLUG_CPU
0148 static void armada_xp_cpu_die(unsigned int cpu)
0149 {
0150     /*
0151      * CPU hotplug is implemented by putting offline CPUs into the
0152      * deep idle sleep state.
0153      */
0154     armada_370_xp_pmsu_idle_enter(true);
0155 }
0156
0157 /*
0158  * We need a dummy function, so that platform_can_cpu_hotplug() knows
0159  * we support CPU hotplug. However, the function does not need to do
0160  * anything, because CPUs going offline can enter the deep idle state
0161  * by themselves, without any help from a still alive CPU.
0162  */
0163 static int armada_xp_cpu_kill(unsigned int cpu)
0164 {
0165     return 1;
0166 }
0167 #endif
0168
0169 const struct smp_operations armada_xp_smp_ops __initconst = {
0170     .smp_init_cpus      = armada_xp_smp_init_cpus,
0171     .smp_prepare_cpus   = armada_xp_smp_prepare_cpus,
0172     .smp_boot_secondary = armada_xp_boot_secondary,
0173     .smp_secondary_init     = armada_xp_secondary_init,
0174 #ifdef CONFIG_HOTPLUG_CPU
0175     .cpu_die        = armada_xp_cpu_die,
0176     .cpu_kill               = armada_xp_cpu_kill,
0177 #endif
0178 };
0179
0180 CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp",
0181               &armada_xp_smp_ops);
0182
0183 #define MV98DX3236_CPU_RESUME_CTRL_REG 0x08
0184 #define MV98DX3236_CPU_RESUME_ADDR_REG 0x04
0185
0186 static const struct of_device_id of_mv98dx3236_resume_table[] = {
0187     {
0188         .compatible = "marvell,98dx3336-resume-ctrl",
0189     },
0190     { /* end of list */ },
0191 };
0192
0193 static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
0194 {
0195     struct device_node *np;
0196     void __iomem *base;
0197     WARN_ON(hw_cpu != 1);
0198
0199     np = of_find_matching_node(NULL, of_mv98dx3236_resume_table);
0200     if (!np)
0201         return -ENODEV;
0202
0203     base = of_io_request_and_map(np, 0, of_node_full_name(np));
0204     of_node_put(np);
0205     if (IS_ERR(base))
0206         return PTR_ERR(base);
0207
0208     writel(0, base + MV98DX3236_CPU_RESUME_CTRL_REG);
0209     writel(__pa_symbol(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG);
0210
0211     iounmap(base);
0212
0213     return 0;
0214 }
0215
0216 static int mv98dx3236_boot_secondary(unsigned int cpu, struct task_struct *idle)
0217 {
0218     int ret, hw_cpu;
0219
0220     hw_cpu = cpu_logical_map(cpu);
0221     mv98dx3236_resume_set_cpu_boot_addr(hw_cpu,
0222                         armada_xp_secondary_startup);
0223
0224     /*
0225      * This is needed to wake up CPUs in the offline state after
0226      * using CPU hotplug.
0227      */
0228     arch_send_wakeup_ipi_mask(cpumask_of(cpu));
0229
0230     /*
0231      * This is needed to take secondary CPUs out of reset on the
0232      * initial boot.
0233      */
0234     ret = mvebu_cpu_reset_deassert(hw_cpu);
0235     if (ret) {
0236         pr_warn("unable to boot CPU: %d\n", ret);
0237         return ret;
0238     }
0239
0240     return 0;
0241 }
0242
0243 static const struct smp_operations mv98dx3236_smp_ops __initconst = {
0244     .smp_init_cpus      = armada_xp_smp_init_cpus,
0245     .smp_prepare_cpus   = armada_xp_smp_prepare_cpus,
0246     .smp_boot_secondary = mv98dx3236_boot_secondary,
0247     .smp_secondary_init     = armada_xp_secondary_init,
0248 #ifdef CONFIG_HOTPLUG_CPU
0249     .cpu_die        = armada_xp_cpu_die,
0250     .cpu_kill               = armada_xp_cpu_kill,
0251 #endif
0252 };
0253
0254 CPU_METHOD_OF_DECLARE(mv98dx3236_smp, "marvell,98dx3236-smp",
0255               &mv98dx3236_smp_ops);