arm/mach-mv78xx0/mv78xx0.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Generic definitions for Marvell MV78xx0 SoC flavors:
0004  *  MV781x0 and MV782x0.
0005  */
0006
0007 #ifndef __ASM_ARCH_MV78XX0_H
0008 #define __ASM_ARCH_MV78XX0_H
0009
0010 #include "irqs.h"
0011
0012 /*
0013  * Marvell MV78xx0 address maps.
0014  *
0015  * phys
0016  * c0000000 PCIe Memory space
0017  * f0800000 PCIe #0 I/O space
0018  * f0900000 PCIe #1 I/O space
0019  * f0a00000 PCIe #2 I/O space
0020  * f0b00000 PCIe #3 I/O space
0021  * f0c00000 PCIe #4 I/O space
0022  * f0d00000 PCIe #5 I/O space
0023  * f0e00000 PCIe #6 I/O space
0024  * f0f00000 PCIe #7 I/O space
0025  * f1000000 on-chip peripheral registers
0026  *
0027  * virt     phys        size
0028  * fe400000 f102x000    16K core-specific peripheral registers
0029  * fee00000 f0800000    64K PCIe #0 I/O space
0030  * fee10000 f0900000    64K PCIe #1 I/O space
0031  * fee20000 f0a00000    64K PCIe #2 I/O space
0032  * fee30000 f0b00000    64K PCIe #3 I/O space
0033  * fee40000 f0c00000    64K PCIe #4 I/O space
0034  * fee50000 f0d00000    64K PCIe #5 I/O space
0035  * fee60000 f0e00000    64K PCIe #6 I/O space
0036  * fee70000 f0f00000    64K PCIe #7 I/O space
0037  * fec00000 f1000000    1M  on-chip peripheral registers
0038  */
0039 #define MV78XX0_CORE0_REGS_PHYS_BASE    0xf1020000
0040 #define MV78XX0_CORE1_REGS_PHYS_BASE    0xf1024000
0041 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
0042 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
0043 #define MV78XX0_CORE_REGS_SIZE      SZ_16K
0044
0045 #define MV78XX0_PCIE_IO_PHYS_BASE(i)    (0xf0800000 + ((i) << 20))
0046 #define MV78XX0_PCIE_IO_SIZE        SZ_1M
0047
0048 #define MV78XX0_REGS_PHYS_BASE      0xf1000000
0049 #define MV78XX0_REGS_VIRT_BASE      IOMEM(0xfec00000)
0050 #define MV78XX0_REGS_SIZE       SZ_1M
0051
0052 #define MV78XX0_PCIE_MEM_PHYS_BASE  0xc0000000
0053 #define MV78XX0_PCIE_MEM_SIZE       0x30000000
0054
0055 /*
0056  * Core-specific peripheral registers.
0057  */
0058 #define BRIDGE_VIRT_BASE    (MV78XX0_CORE_REGS_VIRT_BASE)
0059 #define BRIDGE_PHYS_BASE    (MV78XX0_CORE_REGS_PHYS_BASE)
0060 #define  BRIDGE_WINS_CPU0_BASE  (MV78XX0_CORE0_REGS_PHYS_BASE)
0061 #define  BRIDGE_WINS_CPU1_BASE  (MV78XX0_CORE1_REGS_PHYS_BASE)
0062 #define  BRIDGE_WINS_SZ         (0xA000)
0063
0064 /*
0065  * Register Map
0066  */
0067 #define DDR_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE + 0x00000)
0068 #define DDR_PHYS_BASE           (MV78XX0_REGS_PHYS_BASE + 0x00000)
0069 #define  DDR_WINDOW_CPU0_BASE   (DDR_PHYS_BASE + 0x1500)
0070 #define  DDR_WINDOW_CPU1_BASE   (DDR_PHYS_BASE + 0x1570)
0071 #define  DDR_WINDOW_CPU_SZ      (0x20)
0072
0073 #define DEV_BUS_PHYS_BASE   (MV78XX0_REGS_PHYS_BASE + 0x10000)
0074 #define DEV_BUS_VIRT_BASE   (MV78XX0_REGS_VIRT_BASE + 0x10000)
0075 #define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE + 0x0030)
0076 #define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE + 0x0034)
0077 #define  GPIO_VIRT_BASE     (DEV_BUS_VIRT_BASE + 0x0100)
0078 #define  I2C_0_PHYS_BASE    (DEV_BUS_PHYS_BASE + 0x1000)
0079 #define  I2C_1_PHYS_BASE    (DEV_BUS_PHYS_BASE + 0x1100)
0080 #define  UART0_PHYS_BASE    (DEV_BUS_PHYS_BASE + 0x2000)
0081 #define  UART0_VIRT_BASE    (DEV_BUS_VIRT_BASE + 0x2000)
0082 #define  UART1_PHYS_BASE    (DEV_BUS_PHYS_BASE + 0x2100)
0083 #define  UART1_VIRT_BASE    (DEV_BUS_VIRT_BASE + 0x2100)
0084 #define  UART2_PHYS_BASE    (DEV_BUS_PHYS_BASE + 0x2200)
0085 #define  UART2_VIRT_BASE    (DEV_BUS_VIRT_BASE + 0x2200)
0086 #define  UART3_PHYS_BASE    (DEV_BUS_PHYS_BASE + 0x2300)
0087 #define  UART3_VIRT_BASE    (DEV_BUS_VIRT_BASE + 0x2300)
0088
0089 #define GE10_PHYS_BASE      (MV78XX0_REGS_PHYS_BASE + 0x30000)
0090 #define GE11_PHYS_BASE      (MV78XX0_REGS_PHYS_BASE + 0x34000)
0091
0092 #define PCIE00_VIRT_BASE    (MV78XX0_REGS_VIRT_BASE + 0x40000)
0093 #define PCIE01_VIRT_BASE    (MV78XX0_REGS_VIRT_BASE + 0x44000)
0094 #define PCIE02_VIRT_BASE    (MV78XX0_REGS_VIRT_BASE + 0x48000)
0095 #define PCIE03_VIRT_BASE    (MV78XX0_REGS_VIRT_BASE + 0x4c000)
0096
0097 #define USB0_PHYS_BASE      (MV78XX0_REGS_PHYS_BASE + 0x50000)
0098 #define USB1_PHYS_BASE      (MV78XX0_REGS_PHYS_BASE + 0x51000)
0099 #define USB2_PHYS_BASE      (MV78XX0_REGS_PHYS_BASE + 0x52000)
0100
0101 #define GE00_PHYS_BASE      (MV78XX0_REGS_PHYS_BASE + 0x70000)
0102 #define GE01_PHYS_BASE      (MV78XX0_REGS_PHYS_BASE + 0x74000)
0103
0104 #define PCIE10_VIRT_BASE    (MV78XX0_REGS_VIRT_BASE + 0x80000)
0105 #define PCIE11_VIRT_BASE    (MV78XX0_REGS_VIRT_BASE + 0x84000)
0106 #define PCIE12_VIRT_BASE    (MV78XX0_REGS_VIRT_BASE + 0x88000)
0107 #define PCIE13_VIRT_BASE    (MV78XX0_REGS_VIRT_BASE + 0x8c000)
0108
0109 #define SATA_PHYS_BASE      (MV78XX0_REGS_PHYS_BASE + 0xa0000)
0110
0111 /*
0112  * Supported devices and revisions.
0113  */
0114 #define MV78X00_Z0_DEV_ID   0x6381
0115 #define MV78X00_REV_Z0      1
0116
0117 #define MV78100_DEV_ID      0x7810
0118 #define MV78100_REV_A0      1
0119 #define MV78100_REV_A1      2
0120
0121 #define MV78200_DEV_ID      0x7820
0122 #define MV78200_REV_A0      1
0123
0124 #endif