arm/mach-mv78xx0/irq.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * arch/arm/mach-mv78xx0/irq.c
0004  *
0005  * MV78xx0 IRQ handling.
0006  */
0007 #include <linux/gpio.h>
0008 #include <linux/kernel.h>
0009 #include <linux/irq.h>
0010 #include <linux/io.h>
0011 #include <asm/exception.h>
0012 #include <plat/orion-gpio.h>
0013 #include <plat/irq.h>
0014 #include "bridge-regs.h"
0015 #include "common.h"
0016
0017 static int __initdata gpio0_irqs[4] = {
0018     IRQ_MV78XX0_GPIO_0_7,
0019     IRQ_MV78XX0_GPIO_8_15,
0020     IRQ_MV78XX0_GPIO_16_23,
0021     IRQ_MV78XX0_GPIO_24_31,
0022 };
0023
0024 static void __iomem *mv78xx0_irq_base = IRQ_VIRT_BASE;
0025
0026 static asmlinkage void
0027 __exception_irq_entry mv78xx0_legacy_handle_irq(struct pt_regs *regs)
0028 {
0029     u32 stat;
0030
0031     stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_LOW_OFF);
0032     stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_LOW_OFF);
0033     if (stat) {
0034         unsigned int hwirq = __fls(stat);
0035         handle_IRQ(hwirq, regs);
0036         return;
0037     }
0038     stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_HIGH_OFF);
0039     stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_HIGH_OFF);
0040     if (stat) {
0041         unsigned int hwirq = 32 + __fls(stat);
0042         handle_IRQ(hwirq, regs);
0043         return;
0044     }
0045     stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_ERR_OFF);
0046     stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_ERR_OFF);
0047     if (stat) {
0048         unsigned int hwirq = 64 + __fls(stat);
0049         handle_IRQ(hwirq, regs);
0050         return;
0051     }
0052 }
0053
0054 void __init mv78xx0_init_irq(void)
0055 {
0056     orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
0057     orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
0058     orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
0059
0060     set_handle_irq(mv78xx0_legacy_handle_irq);
0061
0062     /*
0063      * Initialize gpiolib for GPIOs 0-31.  (The GPIO interrupt mask
0064      * registers for core #1 are at an offset of 0x18 from those of
0065      * core #0.)
0066      */
0067     orion_gpio_init(0, 32, GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0,
0068             IRQ_MV78XX0_GPIO_START, gpio0_irqs);
0069 }