arm/mach-mmp/regs-icu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *   Interrupt Control Unit
0004  */
0005
0006 #ifndef __ASM_MACH_ICU_H
0007 #define __ASM_MACH_ICU_H
0008
0009 #include "addr-map.h"
0010
0011 #define ICU_VIRT_BASE   (AXI_VIRT_BASE + 0x82000)
0012 #define ICU_REG(x)  (ICU_VIRT_BASE + (x))
0013
0014 #define ICU2_VIRT_BASE  (AXI_VIRT_BASE + 0x84000)
0015 #define ICU2_REG(x) (ICU2_VIRT_BASE + (x))
0016
0017 #define ICU_INT_CONF(n)     ICU_REG((n) << 2)
0018 #define ICU_INT_CONF_MASK   (0xf)
0019
0020 /************ PXA168/PXA910 (MMP) *********************/
0021 #define ICU_INT_CONF_AP_INT (1 << 6)
0022 #define ICU_INT_CONF_CP_INT (1 << 5)
0023 #define ICU_INT_CONF_IRQ    (1 << 4)
0024
0025 #define ICU_AP_FIQ_SEL_INT_NUM  ICU_REG(0x108)  /* AP FIQ Selected Interrupt */
0026 #define ICU_AP_IRQ_SEL_INT_NUM  ICU_REG(0x10C)  /* AP IRQ Selected Interrupt */
0027 #define ICU_AP_GBL_IRQ_MSK  ICU_REG(0x114)  /* AP Global Interrupt Mask */
0028 #define ICU_INT_STATUS_0    ICU_REG(0x128)  /* Interrupt Stuats 0 */
0029 #define ICU_INT_STATUS_1    ICU_REG(0x12C)  /* Interrupt Status 1 */
0030
0031 /************************** MMP2 ***********************/
0032
0033 /*
0034  * IRQ0/FIQ0 is routed to SP IRQ/FIQ.
0035  * IRQ1 is routed to PJ4 IRQ, and IRQ2 is routes to PJ4 FIQ.
0036  */
0037 #define ICU_INT_ROUTE_SP_IRQ        (1 << 4)
0038 #define ICU_INT_ROUTE_PJ4_IRQ       (1 << 5)
0039 #define ICU_INT_ROUTE_PJ4_FIQ       (1 << 6)
0040
0041 #define MMP2_ICU_PJ4_IRQ_STATUS0    ICU_REG(0x138)
0042 #define MMP2_ICU_PJ4_IRQ_STATUS1    ICU_REG(0x13c)
0043 #define MMP2_ICU_PJ4_FIQ_STATUS0    ICU_REG(0x140)
0044 #define MMP2_ICU_PJ4_FIQ_STATUS1    ICU_REG(0x144)
0045
0046 #define MMP2_ICU_INT4_STATUS        ICU_REG(0x150)
0047 #define MMP2_ICU_INT5_STATUS        ICU_REG(0x154)
0048 #define MMP2_ICU_INT17_STATUS       ICU_REG(0x158)
0049 #define MMP2_ICU_INT35_STATUS       ICU_REG(0x15c)
0050 #define MMP2_ICU_INT51_STATUS       ICU_REG(0x160)
0051
0052 #define MMP2_ICU_INT4_MASK      ICU_REG(0x168)
0053 #define MMP2_ICU_INT5_MASK      ICU_REG(0x16C)
0054 #define MMP2_ICU_INT17_MASK     ICU_REG(0x170)
0055 #define MMP2_ICU_INT35_MASK     ICU_REG(0x174)
0056 #define MMP2_ICU_INT51_MASK     ICU_REG(0x178)
0057
0058 #define MMP2_ICU_SP_IRQ_SEL     ICU_REG(0x100)
0059 #define MMP2_ICU_PJ4_IRQ_SEL        ICU_REG(0x104)
0060 #define MMP2_ICU_PJ4_FIQ_SEL        ICU_REG(0x108)
0061
0062 #define MMP2_ICU_INVERT         ICU_REG(0x164)
0063
0064 #define MMP2_ICU_INV_PMIC       (1 << 0)
0065 #define MMP2_ICU_INV_PERF       (1 << 1)
0066 #define MMP2_ICU_INV_COMMTX     (1 << 2)
0067 #define MMP2_ICU_INV_COMMRX     (1 << 3)
0068
0069 #endif /* __ASM_MACH_ICU_H */