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0009 #ifndef __PXA910_PM_H__
0010 #define __PXA910_PM_H__
0011
0012 #define APMU_MOH_IDLE_CFG APMU_REG(0x0018)
0013 #define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1)
0014 #define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5)
0015 #define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6)
0016 #define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16)
0017 #define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18)
0018 #define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21)
0019 #define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20)
0020
0021 #define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c)
0022 #define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0)
0023
0024 #define MPMU_FCCR MPMU_REG(0x0008)
0025 #define MPMU_APCR MPMU_REG(0x1000)
0026 #define MPMU_APCR_AXISD (1 << 31)
0027 #define MPMU_APCR_DSPSD (1 << 30)
0028 #define MPMU_APCR_SLPEN (1 << 29)
0029 #define MPMU_APCR_DTCMSD (1 << 28)
0030 #define MPMU_APCR_DDRCORSD (1 << 27)
0031 #define MPMU_APCR_APBSD (1 << 26)
0032 #define MPMU_APCR_BBSD (1 << 25)
0033 #define MPMU_APCR_SLPWP0 (1 << 23)
0034 #define MPMU_APCR_SLPWP1 (1 << 22)
0035 #define MPMU_APCR_SLPWP2 (1 << 21)
0036 #define MPMU_APCR_SLPWP3 (1 << 20)
0037 #define MPMU_APCR_VCTCXOSD (1 << 19)
0038 #define MPMU_APCR_SLPWP4 (1 << 18)
0039 #define MPMU_APCR_SLPWP5 (1 << 17)
0040 #define MPMU_APCR_SLPWP6 (1 << 16)
0041 #define MPMU_APCR_SLPWP7 (1 << 15)
0042 #define MPMU_APCR_MSASLPEN (1 << 14)
0043 #define MPMU_APCR_STBYEN (1 << 13)
0044
0045 #define MPMU_AWUCRM MPMU_REG(0x104c)
0046 #define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25)
0047 #define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24)
0048 #define MPMU_AWUCRM_SDH1 (1 << 23)
0049 #define MPMU_AWUCRM_SDH2 (1 << 22)
0050 #define MPMU_AWUCRM_KEYPRESS (1 << 21)
0051 #define MPMU_AWUCRM_TRACKBALL (1 << 20)
0052 #define MPMU_AWUCRM_NEWROTARY (1 << 19)
0053 #define MPMU_AWUCRM_RTC_ALARM (1 << 17)
0054 #define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13)
0055 #define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12)
0056 #define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11)
0057 #define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10)
0058 #define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9)
0059 #define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8)
0060 #define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7))
0061
0062 enum {
0063 POWER_MODE_ACTIVE = 0,
0064 POWER_MODE_CORE_INTIDLE,
0065 POWER_MODE_CORE_EXTIDLE,
0066 POWER_MODE_APPS_IDLE,
0067 POWER_MODE_APPS_SLEEP,
0068 POWER_MODE_SYS_SLEEP,
0069 POWER_MODE_HIBERNATE,
0070 POWER_MODE_UDR,
0071 };
0072
0073 extern int pxa910_set_wake(struct irq_data *data, unsigned int on);
0074
0075 #endif
