arm/mach-mmp/pm-mmp2.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * MMP2 Power Management Routines
0004  *
0005  * (C) Copyright 2010 Marvell International Ltd.
0006  * All Rights Reserved
0007  */
0008
0009 #ifndef __MMP2_PM_H__
0010 #define __MMP2_PM_H__
0011
0012 #include "addr-map.h"
0013
0014 #define APMU_PJ_IDLE_CFG            APMU_REG(0x018)
0015 #define APMU_PJ_IDLE_CFG_PJ_IDLE        (1 << 1)
0016 #define APMU_PJ_IDLE_CFG_PJ_PWRDWN      (1 << 5)
0017 #define APMU_PJ_IDLE_CFG_PWR_SW(x)      ((x) << 16)
0018 #define APMU_PJ_IDLE_CFG_L2_PWR_SW      (1 << 19)
0019 #define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK    (3 << 28)
0020
0021 #define APMU_SRAM_PWR_DWN           APMU_REG(0x08c)
0022
0023 #define MPMU_SCCR               MPMU_REG(0x038)
0024 #define MPMU_PCR_PJ             MPMU_REG(0x1000)
0025 #define MPMU_PCR_PJ_AXISD           (1 << 31)
0026 #define MPMU_PCR_PJ_SLPEN           (1 << 29)
0027 #define MPMU_PCR_PJ_SPSD            (1 << 28)
0028 #define MPMU_PCR_PJ_DDRCORSD            (1 << 27)
0029 #define MPMU_PCR_PJ_APBSD           (1 << 26)
0030 #define MPMU_PCR_PJ_INTCLR          (1 << 24)
0031 #define MPMU_PCR_PJ_SLPWP0          (1 << 23)
0032 #define MPMU_PCR_PJ_SLPWP1          (1 << 22)
0033 #define MPMU_PCR_PJ_SLPWP2          (1 << 21)
0034 #define MPMU_PCR_PJ_SLPWP3          (1 << 20)
0035 #define MPMU_PCR_PJ_VCTCXOSD            (1 << 19)
0036 #define MPMU_PCR_PJ_SLPWP4          (1 << 18)
0037 #define MPMU_PCR_PJ_SLPWP5          (1 << 17)
0038 #define MPMU_PCR_PJ_SLPWP6          (1 << 16)
0039 #define MPMU_PCR_PJ_SLPWP7          (1 << 15)
0040
0041 #define MPMU_PLL2_CTRL1             MPMU_REG(0x0414)
0042 #define MPMU_CGR_PJ             MPMU_REG(0x1024)
0043 #define MPMU_WUCRM_PJ               MPMU_REG(0x104c)
0044 #define MPMU_WUCRM_PJ_WAKEUP(x)         (1 << (x))
0045 #define MPMU_WUCRM_PJ_RTC_ALARM         (1 << 17)
0046
0047 enum {
0048     POWER_MODE_ACTIVE = 0,
0049     POWER_MODE_CORE_INTIDLE,
0050     POWER_MODE_CORE_EXTIDLE,
0051     POWER_MODE_APPS_IDLE,
0052     POWER_MODE_APPS_SLEEP,
0053     POWER_MODE_CHIP_SLEEP,
0054     POWER_MODE_SYS_SLEEP,
0055 };
0056
0057 extern void mmp2_pm_enter_lowpower_mode(int state);
0058 extern int mmp2_set_wake(struct irq_data *d, unsigned int on);
0059 #endif