arm/mach-mmp/platsmp.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
0004  */
0005 #include <linux/io.h>
0006 #include <asm/smp_scu.h>
0007 #include <asm/smp.h>
0008 #include "addr-map.h"
0009
0010 #define SW_BRANCH_VIRT_ADDR CIU_REG(0x24)
0011
0012 static int mmp3_boot_secondary(unsigned int cpu, struct task_struct *idle)
0013 {
0014     /*
0015      * Apparently, the boot ROM on the second core spins on this
0016      * register becoming non-zero and then jumps to the address written
0017      * there. No IPIs involved.
0018      */
0019     __raw_writel(__pa_symbol(secondary_startup), SW_BRANCH_VIRT_ADDR);
0020     return 0;
0021 }
0022
0023 static void mmp3_smp_prepare_cpus(unsigned int max_cpus)
0024 {
0025     scu_enable(SCU_VIRT_BASE);
0026 }
0027
0028 static const struct smp_operations mmp3_smp_ops __initconst = {
0029     .smp_prepare_cpus   = mmp3_smp_prepare_cpus,
0030     .smp_boot_secondary = mmp3_boot_secondary,
0031 };
0032 CPU_METHOD_OF_DECLARE(mmp3_smp, "marvell,mmp3-smp", &mmp3_smp_ops);