arm/mach-mmp/devices.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * linux/arch/arm/mach-mmp/devices.c
0004  */
0005
0006 #include <linux/init.h>
0007 #include <linux/platform_device.h>
0008 #include <linux/dma-mapping.h>
0009 #include <linux/delay.h>
0010
0011 #include <asm/irq.h>
0012 #include "irqs.h"
0013 #include "devices.h"
0014 #include <linux/soc/mmp/cputype.h>
0015 #include "regs-usb.h"
0016
0017 int __init mmp_register_device(struct mmp_device_desc *desc,
0018                 void *data, size_t size)
0019 {
0020     struct platform_device *pdev;
0021     struct resource res[2 + MAX_RESOURCE_DMA];
0022     int i, ret = 0, nres = 0;
0023
0024     pdev = platform_device_alloc(desc->drv_name, desc->id);
0025     if (pdev == NULL)
0026         return -ENOMEM;
0027
0028     pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
0029
0030     memset(res, 0, sizeof(res));
0031
0032     if (desc->start != -1ul && desc->size > 0) {
0033         res[nres].start = desc->start;
0034         res[nres].end   = desc->start + desc->size - 1;
0035         res[nres].flags = IORESOURCE_MEM;
0036         nres++;
0037     }
0038
0039     if (desc->irq != NO_IRQ) {
0040         res[nres].start = desc->irq;
0041         res[nres].end   = desc->irq;
0042         res[nres].flags = IORESOURCE_IRQ;
0043         nres++;
0044     }
0045
0046     for (i = 0; i < MAX_RESOURCE_DMA; i++, nres++) {
0047         if (desc->dma[i] == 0)
0048             break;
0049
0050         res[nres].start = desc->dma[i];
0051         res[nres].end   = desc->dma[i];
0052         res[nres].flags = IORESOURCE_DMA;
0053     }
0054
0055     ret = platform_device_add_resources(pdev, res, nres);
0056     if (ret) {
0057         platform_device_put(pdev);
0058         return ret;
0059     }
0060
0061     if (data && size) {
0062         ret = platform_device_add_data(pdev, data, size);
0063         if (ret) {
0064             platform_device_put(pdev);
0065             return ret;
0066         }
0067     }
0068
0069     return platform_device_add(pdev);
0070 }
0071
0072 #if IS_ENABLED(CONFIG_USB) || IS_ENABLED(CONFIG_USB_GADGET)
0073 #if IS_ENABLED(CONFIG_USB_MV_UDC) || IS_ENABLED(CONFIG_USB_EHCI_MV)
0074 #if IS_ENABLED(CONFIG_CPU_PXA910) || IS_ENABLED(CONFIG_CPU_PXA168)
0075
0076 /*****************************************************************************
0077  * The registers read/write routines
0078  *****************************************************************************/
0079
0080 static unsigned int u2o_get(void __iomem *base, unsigned int offset)
0081 {
0082     return readl_relaxed(base + offset);
0083 }
0084
0085 static void u2o_set(void __iomem *base, unsigned int offset,
0086         unsigned int value)
0087 {
0088     u32 reg;
0089
0090     reg = readl_relaxed(base + offset);
0091     reg |= value;
0092     writel_relaxed(reg, base + offset);
0093     readl_relaxed(base + offset);
0094 }
0095
0096 static void u2o_clear(void __iomem *base, unsigned int offset,
0097         unsigned int value)
0098 {
0099     u32 reg;
0100
0101     reg = readl_relaxed(base + offset);
0102     reg &= ~value;
0103     writel_relaxed(reg, base + offset);
0104     readl_relaxed(base + offset);
0105 }
0106
0107 static void u2o_write(void __iomem *base, unsigned int offset,
0108         unsigned int value)
0109 {
0110     writel_relaxed(value, base + offset);
0111     readl_relaxed(base + offset);
0112 }
0113
0114
0115 static DEFINE_MUTEX(phy_lock);
0116 static int phy_init_cnt;
0117
0118 static int usb_phy_init_internal(void __iomem *base)
0119 {
0120     int loops;
0121
0122     pr_info("Init usb phy!!!\n");
0123
0124     /* Initialize the USB PHY power */
0125     if (cpu_is_pxa910()) {
0126         u2o_set(base, UTMI_CTRL, (1<<UTMI_CTRL_INPKT_DELAY_SOF_SHIFT)
0127             | (1<<UTMI_CTRL_PU_REF_SHIFT));
0128     }
0129
0130     u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT);
0131     u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT);
0132
0133     /* UTMI_PLL settings */
0134     u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK
0135         | UTMI_PLL_PLLVDD12_MASK | UTMI_PLL_PLLCALI12_MASK
0136         | UTMI_PLL_FBDIV_MASK | UTMI_PLL_REFDIV_MASK
0137         | UTMI_PLL_ICP_MASK | UTMI_PLL_KVCO_MASK);
0138
0139     u2o_set(base, UTMI_PLL, 0xee<<UTMI_PLL_FBDIV_SHIFT
0140         | 0xb<<UTMI_PLL_REFDIV_SHIFT | 3<<UTMI_PLL_PLLVDD18_SHIFT
0141         | 3<<UTMI_PLL_PLLVDD12_SHIFT | 3<<UTMI_PLL_PLLCALI12_SHIFT
0142         | 1<<UTMI_PLL_ICP_SHIFT | 3<<UTMI_PLL_KVCO_SHIFT);
0143
0144     /* UTMI_TX */
0145     u2o_clear(base, UTMI_TX, UTMI_TX_REG_EXT_FS_RCAL_EN_MASK
0146         | UTMI_TX_TXVDD12_MASK | UTMI_TX_CK60_PHSEL_MASK
0147         | UTMI_TX_IMPCAL_VTH_MASK | UTMI_TX_REG_EXT_FS_RCAL_MASK
0148         | UTMI_TX_AMP_MASK);
0149     u2o_set(base, UTMI_TX, 3<<UTMI_TX_TXVDD12_SHIFT
0150         | 4<<UTMI_TX_CK60_PHSEL_SHIFT | 4<<UTMI_TX_IMPCAL_VTH_SHIFT
0151         | 8<<UTMI_TX_REG_EXT_FS_RCAL_SHIFT | 3<<UTMI_TX_AMP_SHIFT);
0152
0153     /* UTMI_RX */
0154     u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK
0155         | UTMI_REG_SQ_LENGTH_MASK);
0156     u2o_set(base, UTMI_RX, 7<<UTMI_RX_SQ_THRESH_SHIFT
0157         | 2<<UTMI_REG_SQ_LENGTH_SHIFT);
0158
0159     /* UTMI_IVREF */
0160     if (cpu_is_pxa168())
0161         /* fixing Microsoft Altair board interface with NEC hub issue -
0162          * Set UTMI_IVREF from 0x4a3 to 0x4bf */
0163         u2o_write(base, UTMI_IVREF, 0x4bf);
0164
0165     /* toggle VCOCAL_START bit of UTMI_PLL */
0166     udelay(200);
0167     u2o_set(base, UTMI_PLL, VCOCAL_START);
0168     udelay(40);
0169     u2o_clear(base, UTMI_PLL, VCOCAL_START);
0170
0171     /* toggle REG_RCAL_START bit of UTMI_TX */
0172     udelay(400);
0173     u2o_set(base, UTMI_TX, REG_RCAL_START);
0174     udelay(40);
0175     u2o_clear(base, UTMI_TX, REG_RCAL_START);
0176     udelay(400);
0177
0178     /* Make sure PHY PLL is ready */
0179     loops = 0;
0180     while ((u2o_get(base, UTMI_PLL) & PLL_READY) == 0) {
0181         mdelay(1);
0182         loops++;
0183         if (loops > 100) {
0184             printk(KERN_WARNING "calibrate timeout, UTMI_PLL %x\n",
0185                 u2o_get(base, UTMI_PLL));
0186             break;
0187         }
0188     }
0189
0190     if (cpu_is_pxa168()) {
0191         u2o_set(base, UTMI_RESERVE, 1 << 5);
0192         /* Turn on UTMI PHY OTG extension */
0193         u2o_write(base, UTMI_OTG_ADDON, 1);
0194     }
0195
0196     return 0;
0197 }
0198
0199 static int usb_phy_deinit_internal(void __iomem *base)
0200 {
0201     pr_info("Deinit usb phy!!!\n");
0202
0203     if (cpu_is_pxa168())
0204         u2o_clear(base, UTMI_OTG_ADDON, UTMI_OTG_ADDON_OTG_ON);
0205
0206     u2o_clear(base, UTMI_CTRL, UTMI_CTRL_RXBUF_PDWN);
0207     u2o_clear(base, UTMI_CTRL, UTMI_CTRL_TXBUF_PDWN);
0208     u2o_clear(base, UTMI_CTRL, UTMI_CTRL_USB_CLK_EN);
0209     u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT);
0210     u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT);
0211
0212     return 0;
0213 }
0214
0215 int pxa_usb_phy_init(void __iomem *phy_reg)
0216 {
0217     mutex_lock(&phy_lock);
0218     if (phy_init_cnt++ == 0)
0219         usb_phy_init_internal(phy_reg);
0220     mutex_unlock(&phy_lock);
0221     return 0;
0222 }
0223
0224 void pxa_usb_phy_deinit(void __iomem *phy_reg)
0225 {
0226     WARN_ON(phy_init_cnt == 0);
0227
0228     mutex_lock(&phy_lock);
0229     if (--phy_init_cnt == 0)
0230         usb_phy_deinit_internal(phy_reg);
0231     mutex_unlock(&phy_lock);
0232 }
0233 #endif
0234 #endif
0235 #endif
0236
0237 #if IS_ENABLED(CONFIG_USB_SUPPORT)
0238 static u64 __maybe_unused usb_dma_mask = ~(u32)0;
0239
0240 #if IS_ENABLED(CONFIG_PHY_PXA_USB)
0241 struct resource pxa168_usb_phy_resources[] = {
0242     [0] = {
0243         .start  = PXA168_U2O_PHYBASE,
0244         .end    = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
0245         .flags  = IORESOURCE_MEM,
0246     },
0247 };
0248
0249 struct platform_device pxa168_device_usb_phy = {
0250     .name       = "pxa-usb-phy",
0251     .id     = -1,
0252     .resource   = pxa168_usb_phy_resources,
0253     .num_resources  = ARRAY_SIZE(pxa168_usb_phy_resources),
0254     .dev        =  {
0255         .dma_mask   = &usb_dma_mask,
0256         .coherent_dma_mask = 0xffffffff,
0257     }
0258 };
0259 #endif /* CONFIG_PHY_PXA_USB */
0260
0261 #if IS_ENABLED(CONFIG_USB_MV_UDC)
0262 struct resource pxa168_u2o_resources[] = {
0263     /* regbase */
0264     [0] = {
0265         .start  = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
0266         .end    = PXA168_U2O_REGBASE + USB_REG_RANGE,
0267         .flags  = IORESOURCE_MEM,
0268         .name   = "capregs",
0269     },
0270     /* phybase */
0271     [1] = {
0272         .start  = PXA168_U2O_PHYBASE,
0273         .end    = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
0274         .flags  = IORESOURCE_MEM,
0275         .name   = "phyregs",
0276     },
0277     [2] = {
0278         .start  = IRQ_PXA168_USB1,
0279         .end    = IRQ_PXA168_USB1,
0280         .flags  = IORESOURCE_IRQ,
0281     },
0282 };
0283
0284 struct platform_device pxa168_device_u2o = {
0285     .name       = "mv-udc",
0286     .id     = -1,
0287     .resource   = pxa168_u2o_resources,
0288     .num_resources  = ARRAY_SIZE(pxa168_u2o_resources),
0289     .dev        =  {
0290         .dma_mask   = &usb_dma_mask,
0291         .coherent_dma_mask = 0xffffffff,
0292     }
0293 };
0294 #endif /* CONFIG_USB_MV_UDC */
0295
0296 #if IS_ENABLED(CONFIG_USB_EHCI_MV_U2O)
0297 struct resource pxa168_u2oehci_resources[] = {
0298     [0] = {
0299         .start  = PXA168_U2O_REGBASE,
0300         .end    = PXA168_U2O_REGBASE + USB_REG_RANGE,
0301         .flags  = IORESOURCE_MEM,
0302     },
0303     [1] = {
0304         .start  = IRQ_PXA168_USB1,
0305         .end    = IRQ_PXA168_USB1,
0306         .flags  = IORESOURCE_IRQ,
0307     },
0308 };
0309
0310 struct platform_device pxa168_device_u2oehci = {
0311     .name       = "pxa-u2oehci",
0312     .id     = -1,
0313     .dev        = {
0314         .dma_mask       = &usb_dma_mask,
0315         .coherent_dma_mask  = 0xffffffff,
0316     },
0317
0318     .num_resources  = ARRAY_SIZE(pxa168_u2oehci_resources),
0319     .resource   = pxa168_u2oehci_resources,
0320 };
0321 #endif
0322
0323 #if IS_ENABLED(CONFIG_USB_MV_OTG)
0324 struct resource pxa168_u2ootg_resources[] = {
0325     /* regbase */
0326     [0] = {
0327         .start  = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
0328         .end    = PXA168_U2O_REGBASE + USB_REG_RANGE,
0329         .flags  = IORESOURCE_MEM,
0330         .name   = "capregs",
0331     },
0332     /* phybase */
0333     [1] = {
0334         .start  = PXA168_U2O_PHYBASE,
0335         .end    = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
0336         .flags  = IORESOURCE_MEM,
0337         .name   = "phyregs",
0338     },
0339     [2] = {
0340         .start  = IRQ_PXA168_USB1,
0341         .end    = IRQ_PXA168_USB1,
0342         .flags  = IORESOURCE_IRQ,
0343     },
0344 };
0345
0346 struct platform_device pxa168_device_u2ootg = {
0347     .name       = "mv-otg",
0348     .id     = -1,
0349     .dev  = {
0350         .dma_mask          = &usb_dma_mask,
0351         .coherent_dma_mask = 0xffffffff,
0352     },
0353
0354     .num_resources  = ARRAY_SIZE(pxa168_u2ootg_resources),
0355     .resource      = pxa168_u2ootg_resources,
0356 };
0357 #endif /* CONFIG_USB_MV_OTG */
0358
0359 #endif