arm/mach-mmp/addr-map.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *   Common address map definitions
0004  */
0005
0006 #ifndef __ASM_MACH_ADDR_MAP_H
0007 #define __ASM_MACH_ADDR_MAP_H
0008
0009 /* APB - Application Subsystem Peripheral Bus
0010  *
0011  * NOTE: the DMA controller registers are actually on the AXI fabric #1
0012  * slave port to AHB/APB bridge, due to its close relationship to those
0013  * peripherals on APB, let's count it into the ABP mapping area.
0014  */
0015 #define APB_PHYS_BASE       0xd4000000
0016 #define APB_VIRT_BASE       IOMEM(0xfe000000)
0017 #define APB_PHYS_SIZE       0x00200000
0018
0019 #define AXI_PHYS_BASE       0xd4200000
0020 #define AXI_VIRT_BASE       IOMEM(0xfe200000)
0021 #define AXI_PHYS_SIZE       0x00200000
0022
0023 #define PGU_PHYS_BASE       0xe0000000
0024 #define PGU_VIRT_BASE       IOMEM(0xfe400000)
0025 #define PGU_PHYS_SIZE       0x00100000
0026
0027 /* Static Memory Controller - Chip Select 0 and 1 */
0028 #define SMC_CS0_PHYS_BASE   0x80000000
0029 #define SMC_CS0_PHYS_SIZE   0x10000000
0030 #define SMC_CS1_PHYS_BASE   0x90000000
0031 #define SMC_CS1_PHYS_SIZE   0x10000000
0032
0033 #define APMU_VIRT_BASE      (AXI_VIRT_BASE + 0x82800)
0034 #define APMU_REG(x)     (APMU_VIRT_BASE + (x))
0035
0036 #define APBC_VIRT_BASE      (APB_VIRT_BASE + 0x015000)
0037 #define APBC_REG(x)     (APBC_VIRT_BASE + (x))
0038
0039 #define MPMU_VIRT_BASE      (APB_VIRT_BASE + 0x50000)
0040 #define MPMU_REG(x)     (MPMU_VIRT_BASE + (x))
0041
0042 #define CIU_VIRT_BASE       (AXI_VIRT_BASE + 0x82c00)
0043 #define CIU_REG(x)      (CIU_VIRT_BASE + (x))
0044
0045 #define SCU_VIRT_BASE       (PGU_VIRT_BASE)
0046 #define SCU_REG(x)      (SCU_VIRT_BASE + (x))
0047
0048 #endif /* __ASM_MACH_ADDR_MAP_H */