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0010 #include <linux/linkage.h>
0011 #include <asm/assembler.h>
0012 #include "lpc32xx.h"
0013
0014
0015 #define WORK1_REG r0
0016 #define WORK2_REG r1
0017 #define SAVED_HCLK_DIV_REG r2
0018 #define SAVED_HCLK_PLL_REG r3
0019 #define SAVED_DRAM_CLKCTRL_REG r4
0020 #define SAVED_PWR_CTRL_REG r5
0021 #define CLKPWRBASE_REG r6
0022 #define EMCBASE_REG r7
0023
0024 #define LPC32XX_EMC_STATUS_OFFS 0x04
0025 #define LPC32XX_EMC_STATUS_BUSY 0x1
0026 #define LPC32XX_EMC_STATUS_SELF_RFSH 0x4
0027
0028 #define LPC32XX_CLKPWR_PWR_CTRL_OFFS 0x44
0029 #define LPC32XX_CLKPWR_HCLK_DIV_OFFS 0x40
0030 #define LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS 0x58
0031
0032 #define CLKPWR_PCLK_DIV_MASK 0xFFFFFE7F
0033
0034 .text
0035
0036 ENTRY(lpc32xx_sys_suspend)
0037 @ Save a copy of the used registers in IRAM, r0 is corrupted
0038 adr r0, tmp_stack_end
0039 stmfd r0!, {r3 - r7, sp, lr}
0040
0041 @ Load a few common register addresses
0042 adr WORK1_REG, reg_bases
0043 ldr CLKPWRBASE_REG, [WORK1_REG, #0]
0044 ldr EMCBASE_REG, [WORK1_REG, #4]
0045
0046 ldr SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
0047 #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
0048 orr WORK1_REG, SAVED_PWR_CTRL_REG, #LPC32XX_CLKPWR_SDRAM_SELF_RFSH
0049
0050 @ Wait for SDRAM busy status to go busy and then idle
0051 @ This guarantees a small windows where DRAM isn't busy
0052 1:
0053 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
0054 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
0055 cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
0056 bne 1b @ Branch while idle
0057 2:
0058 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
0059 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
0060 cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
0061 beq 2b @ Branch until idle
0062
0063 @ Setup self-refresh with support for manual exit of
0064 @ self-refresh mode
0065 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
0066 orr WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
0067 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
0068 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
0069
0070 @ Wait for self-refresh acknowledge, clocks to the DRAM device
0071 @ will automatically stop on start of self-refresh
0072 3:
0073 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
0074 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
0075 cmp WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
0076 bne 3b @ Branch until self-refresh mode starts
0077
0078 @ Enter direct-run mode from run mode
0079 bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_SELECT_RUN_MODE
0080 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
0081
0082 @ Safe disable of DRAM clock in EMC block, prevents DDR sync
0083 @ issues on restart
0084 ldr SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
0085 #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
0086 and WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK
0087 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
0088
0089 @ Save HCLK PLL state and disable HCLK PLL
0090 ldr SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
0091 #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
0092 bic WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
0093 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
0094
0095 @ Enter stop mode until an enabled event occurs
0096 orr WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
0097 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
0098 .rept 9
0099 nop
0100 .endr
0101
0102 @ Clear stop status
0103 bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
0104
0105 @ Restore original HCLK PLL value and wait for PLL lock
0106 str SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
0107 #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
0108 4:
0109 ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
0110 and WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
0111 bne 4b
0112
0113 @ Re-enter run mode with self-refresh flag cleared, but no DRAM
0114 @ update yet. DRAM is still in self-refresh
0115 str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
0116 #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
0117
0118 @ Restore original DRAM clock mode to restore DRAM clocks
0119 str SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
0120 #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
0121
0122 @ Clear self-refresh mode
0123 orr WORK1_REG, SAVED_PWR_CTRL_REG,\
0124 #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
0125 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
0126 str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
0127 #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
0128
0129 @ Wait for EMC to clear self-refresh mode
0130 5:
0131 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
0132 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
0133 bne 5b @ Branch until self-refresh has exited
0134
0135 @ restore regs and return
0136 adr r0, tmp_stack
0137 ldmfd r0!, {r3 - r7, sp, pc}
0138
0139 reg_bases:
0140 .long IO_ADDRESS(LPC32XX_CLK_PM_BASE)
0141 .long IO_ADDRESS(LPC32XX_EMC_BASE)
0142
0143 tmp_stack:
0144 .long 0, 0, 0, 0, 0, 0, 0
0145 tmp_stack_end:
0146
0147 ENTRY(lpc32xx_sys_suspend_sz)
0148 .word . - lpc32xx_sys_suspend
