arm/mach-lpc32xx/pm.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * arch/arm/mach-lpc32xx/pm.c
0004  *
0005  * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
0006  * Modified by Kevin Wells <kevin.wells@nxp.com>
0007  *
0008  * 2005 (c) MontaVista Software, Inc.
0009  */
0010
0011 /*
0012  * LPC32XX CPU and system power management
0013  *
0014  * The LPC32XX has three CPU modes for controlling system power: run,
0015  * direct-run, and halt modes. When switching between halt and run modes,
0016  * the CPU transistions through direct-run mode. For Linux, direct-run
0017  * mode is not used in normal operation. Halt mode is used when the
0018  * system is fully suspended.
0019  *
0020  * Run mode:
0021  * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
0022  * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
0023  * the HCLK_PLL rate. Linux runs in this mode.
0024  *
0025  * Direct-run mode:
0026  * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
0027  * SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK
0028  * source or the frequency of the main oscillator. In this mode, the
0029  * HCLK_PLL can be safely enabled, changed, or disabled.
0030  *
0031  * Halt mode:
0032  * SYSCLK is gated off and the CPU and system clocks are halted.
0033  * Peripherals based on the 32KHz oscillator clock (ie, RTC, touch,
0034  * key scanner, etc.) still operate if enabled. In this state, an enabled
0035  * system event (ie, GPIO state change, RTC match, key press, etc.) will
0036  * wake the system up back into direct-run mode.
0037  *
0038  * DRAM refresh
0039  * DRAM clocking and refresh are slightly different for systems with DDR
0040  * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
0041  * SDRAM will still be accessible in direct-run mode. In DDR based systems,
0042  * a transition to direct-run mode will stop all DDR accesses (no clocks).
0043  * Because of this, the code to switch power modes and the code to enter
0044  * and exit DRAM self-refresh modes must not be executed in DRAM. A small
0045  * section of IRAM is used instead for this.
0046  *
0047  * Suspend is handled with the following logic:
0048  *  Backup a small area of IRAM used for the suspend code
0049  *  Copy suspend code to IRAM
0050  *  Transfer control to code in IRAM
0051  *  Places DRAMs in self-refresh mode
0052  *  Enter direct-run mode
0053  *  Save state of HCLK_PLL PLL
0054  *  Disable HCLK_PLL PLL
0055  *  Enter halt mode - CPU and buses will stop
0056  *  System enters direct-run mode when an enabled event occurs
0057  *  HCLK PLL state is restored
0058  *  Run mode is entered
0059  *  DRAMS are placed back into normal mode
0060  *  Code execution returns from IRAM
0061  *  IRAM code are used for suspend is restored
0062  *  Suspend mode is exited
0063  */
0064
0065 #include <linux/suspend.h>
0066 #include <linux/io.h>
0067 #include <linux/slab.h>
0068
0069 #include <asm/cacheflush.h>
0070
0071 #include "lpc32xx.h"
0072 #include "common.h"
0073
0074 #define TEMP_IRAM_AREA  IO_ADDRESS(LPC32XX_IRAM_BASE)
0075
0076 /*
0077  * Both STANDBY and MEM suspend states are handled the same with no
0078  * loss of CPU or memory state
0079  */
0080 static int lpc32xx_pm_enter(suspend_state_t state)
0081 {
0082     int (*lpc32xx_suspend_ptr) (void);
0083     void *iram_swap_area;
0084
0085     /* Allocate some space for temporary IRAM storage */
0086     iram_swap_area = kmemdup((void *)TEMP_IRAM_AREA,
0087                  lpc32xx_sys_suspend_sz, GFP_KERNEL);
0088     if (!iram_swap_area)
0089         return -ENOMEM;
0090
0091     /*
0092      * Copy code to suspend system into IRAM. The suspend code
0093      * needs to run from IRAM as DRAM may no longer be available
0094      * when the PLL is stopped.
0095      */
0096     memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend,
0097         lpc32xx_sys_suspend_sz);
0098     flush_icache_range((unsigned long)TEMP_IRAM_AREA,
0099         (unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz);
0100
0101     /* Transfer to suspend code in IRAM */
0102     lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA;
0103     flush_cache_all();
0104     (void) lpc32xx_suspend_ptr();
0105
0106     /* Restore original IRAM contents */
0107     memcpy((void *) TEMP_IRAM_AREA, iram_swap_area,
0108         lpc32xx_sys_suspend_sz);
0109
0110     kfree(iram_swap_area);
0111
0112     return 0;
0113 }
0114
0115 static const struct platform_suspend_ops lpc32xx_pm_ops = {
0116     .valid  = suspend_valid_only_mem,
0117     .enter  = lpc32xx_pm_enter,
0118 };
0119
0120 #define EMC_DYN_MEM_CTRL_OFS 0x20
0121 #define EMC_SRMMC           (1 << 3)
0122 #define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
0123 static int __init lpc32xx_pm_init(void)
0124 {
0125     /*
0126      * Setup SDRAM self-refresh clock to automatically disable o
0127      * start of self-refresh. This only needs to be done once.
0128      */
0129     __raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
0130
0131     suspend_set_ops(&lpc32xx_pm_ops);
0132
0133     return 0;
0134 }
0135 arch_initcall(lpc32xx_pm_init);