arm/mach-lpc32xx/phy3250.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Platform support for LPC32xx SoC
0004  *
0005  * Author: Kevin Wells <kevin.wells@nxp.com>
0006  *
0007  * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
0008  * Copyright (C) 2010 NXP Semiconductors
0009  */
0010
0011 #include <linux/amba/pl08x.h>
0012 #include <linux/mtd/lpc32xx_mlc.h>
0013 #include <linux/mtd/lpc32xx_slc.h>
0014 #include <linux/of_platform.h>
0015
0016 #include <asm/mach/arch.h>
0017 #include "common.h"
0018
0019 static struct pl08x_channel_data pl08x_slave_channels[] = {
0020     {
0021         .bus_id = "nand-slc",
0022         .min_signal = 1, /* SLC NAND Flash */
0023         .max_signal = 1,
0024         .periph_buses = PL08X_AHB1,
0025     },
0026     {
0027         .bus_id = "nand-mlc",
0028         .min_signal = 12, /* MLC NAND Flash */
0029         .max_signal = 12,
0030         .periph_buses = PL08X_AHB1,
0031     },
0032 };
0033
0034 static int pl08x_get_signal(const struct pl08x_channel_data *cd)
0035 {
0036     return cd->min_signal;
0037 }
0038
0039 static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch)
0040 {
0041 }
0042
0043 static struct pl08x_platform_data pl08x_pd = {
0044     /* Some reasonable memcpy defaults */
0045     .memcpy_burst_size = PL08X_BURST_SZ_256,
0046     .memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,
0047     .slave_channels = &pl08x_slave_channels[0],
0048     .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
0049     .get_xfer_signal = pl08x_get_signal,
0050     .put_xfer_signal = pl08x_put_signal,
0051     .lli_buses = PL08X_AHB1,
0052     .mem_buses = PL08X_AHB1,
0053 };
0054
0055 static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
0056     .dma_filter = pl08x_filter_id,
0057 };
0058
0059 static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
0060     .dma_filter = pl08x_filter_id,
0061 };
0062
0063 static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
0064     OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
0065     OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
0066                &lpc32xx_slc_data),
0067     OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
0068                &lpc32xx_mlc_data),
0069     { }
0070 };
0071
0072 static void __init lpc3250_machine_init(void)
0073 {
0074     lpc32xx_serial_init();
0075
0076     of_platform_default_populate(NULL, lpc32xx_auxdata_lookup, NULL);
0077 }
0078
0079 static const char *const lpc32xx_dt_compat[] __initconst = {
0080     "nxp,lpc3220",
0081     "nxp,lpc3230",
0082     "nxp,lpc3240",
0083     "nxp,lpc3250",
0084     NULL
0085 };
0086
0087 DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
0088     .atag_offset    = 0x100,
0089     .map_io     = lpc32xx_map_io,
0090     .init_machine   = lpc3250_machine_init,
0091     .dt_compat  = lpc32xx_dt_compat,
0092 MACHINE_END