arm/mach-lpc32xx/common.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * arch/arm/mach-lpc32xx/common.c
0004  *
0005  * Author: Kevin Wells <kevin.wells@nxp.com>
0006  *
0007  * Copyright (C) 2010 NXP Semiconductors
0008  */
0009
0010 #include <linux/init.h>
0011 #include <linux/soc/nxp/lpc32xx-misc.h>
0012
0013 #include <asm/mach/map.h>
0014 #include <asm/system_info.h>
0015
0016 #include "lpc32xx.h"
0017 #include "common.h"
0018
0019 /*
0020  * Returns the unique ID for the device
0021  */
0022 void lpc32xx_get_uid(u32 devid[4])
0023 {
0024     int i;
0025
0026     for (i = 0; i < 4; i++)
0027         devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
0028 }
0029
0030 /*
0031  * Detects and returns IRAM size for the device variation
0032  */
0033 #define LPC32XX_IRAM_BANK_SIZE SZ_128K
0034 static u32 iram_size;
0035 u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr)
0036 {
0037     if (iram_size == 0) {
0038         u32 savedval1, savedval2;
0039         void __iomem *iramptr1, *iramptr2;
0040
0041         iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
0042         iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
0043         savedval1 = __raw_readl(iramptr1);
0044         savedval2 = __raw_readl(iramptr2);
0045
0046         if (savedval1 == savedval2) {
0047             __raw_writel(savedval2 + 1, iramptr2);
0048             if (__raw_readl(iramptr1) == savedval2 + 1)
0049                 iram_size = LPC32XX_IRAM_BANK_SIZE;
0050             else
0051                 iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
0052             __raw_writel(savedval2, iramptr2);
0053         } else
0054             iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
0055     }
0056     if (dmaaddr)
0057         *dmaaddr = LPC32XX_IRAM_BASE;
0058     if (mapbase)
0059         *mapbase = io_p2v(LPC32XX_IRAM_BASE);
0060
0061     return iram_size;
0062 }
0063 EXPORT_SYMBOL_GPL(lpc32xx_return_iram);
0064
0065 void lpc32xx_set_phy_interface_mode(phy_interface_t mode)
0066 {
0067     u32 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
0068     tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
0069     if (mode == PHY_INTERFACE_MODE_MII)
0070         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS;
0071     else
0072         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
0073     __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
0074 }
0075 EXPORT_SYMBOL_GPL(lpc32xx_set_phy_interface_mode);
0076
0077 static struct map_desc lpc32xx_io_desc[] __initdata = {
0078     {
0079         .virtual    = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),
0080         .pfn        = __phys_to_pfn(LPC32XX_AHB0_START),
0081         .length     = LPC32XX_AHB0_SIZE,
0082         .type       = MT_DEVICE
0083     },
0084     {
0085         .virtual    = (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START),
0086         .pfn        = __phys_to_pfn(LPC32XX_AHB1_START),
0087         .length     = LPC32XX_AHB1_SIZE,
0088         .type       = MT_DEVICE
0089     },
0090     {
0091         .virtual    = (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START),
0092         .pfn        = __phys_to_pfn(LPC32XX_FABAPB_START),
0093         .length     = LPC32XX_FABAPB_SIZE,
0094         .type       = MT_DEVICE
0095     },
0096     {
0097         .virtual    = (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE),
0098         .pfn        = __phys_to_pfn(LPC32XX_IRAM_BASE),
0099         .length     = (LPC32XX_IRAM_BANK_SIZE * 2),
0100         .type       = MT_DEVICE
0101     },
0102 };
0103
0104 void __init lpc32xx_map_io(void)
0105 {
0106     iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
0107 }
0108
0109 static int __init lpc32xx_check_uid(void)
0110 {
0111     u32 uid[4];
0112
0113     lpc32xx_get_uid(uid);
0114
0115     printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
0116         uid[3], uid[2], uid[1], uid[0]);
0117
0118     if (!system_serial_low && !system_serial_high) {
0119         system_serial_low = uid[0];
0120         system_serial_high = uid[1];
0121     }
0122
0123     return 1;
0124 }
0125 arch_initcall(lpc32xx_check_uid);