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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Intel IOP32X and IOP33X register definitions
0004  *
0005  * Author: Rory Bolt <rorybolt@pacbell.net>
0006  * Copyright (C) 2002 Rory Bolt
0007  * Copyright (C) 2004 Intel Corp.
0008  */
0009 
0010 #ifndef __IOP3XX_H
0011 #define __IOP3XX_H
0012 
0013 /*
0014  * Peripherals that are shared between the iop32x and iop33x but
0015  * located at different addresses.
0016  */
0017 #define IOP3XX_TIMER_REG(reg)   (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
0018 
0019 #include "iop3xx.h"
0020 
0021 /* ATU Parameters
0022  * set up a 1:1 bus to physical ram relationship
0023  * w/ physical ram on top of pci in the memory map
0024  */
0025 #define IOP32X_MAX_RAM_SIZE            0x40000000UL
0026 #define IOP3XX_MAX_RAM_SIZE            IOP32X_MAX_RAM_SIZE
0027 #define IOP3XX_PCI_LOWER_MEM_BA        0x80000000
0028 
0029 /*
0030  * IOP3XX GPIO handling
0031  */
0032 #define IOP3XX_GPIO_LINE(x) (x)
0033 
0034 #ifndef __ASSEMBLY__
0035 extern int init_atu;
0036 extern int iop3xx_get_init_atu(void);
0037 #endif
0038 
0039 
0040 /*
0041  * IOP3XX processor registers
0042  */
0043 #define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
0044 #define IOP3XX_PERIPHERAL_VIRT_BASE 0xfedfe000
0045 #define IOP3XX_PERIPHERAL_SIZE      0x00002000
0046 #define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
0047                     IOP3XX_PERIPHERAL_SIZE - 1)
0048 #define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
0049                     IOP3XX_PERIPHERAL_SIZE - 1)
0050 #define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
0051                     (IOP3XX_PERIPHERAL_PHYS_BASE\
0052                     - IOP3XX_PERIPHERAL_VIRT_BASE))
0053 #define IOP3XX_REG_ADDR(reg)        (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
0054 
0055 /* Address Translation Unit  */
0056 #define IOP3XX_ATUVID       (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
0057 #define IOP3XX_ATUDID       (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
0058 #define IOP3XX_ATUCMD       (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
0059 #define IOP3XX_ATUSR        (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
0060 #define IOP3XX_ATURID       (volatile u8  *)IOP3XX_REG_ADDR(0x0108)
0061 #define IOP3XX_ATUCCR       (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
0062 #define IOP3XX_ATUCLSR      (volatile u8  *)IOP3XX_REG_ADDR(0x010c)
0063 #define IOP3XX_ATULT        (volatile u8  *)IOP3XX_REG_ADDR(0x010d)
0064 #define IOP3XX_ATUHTR       (volatile u8  *)IOP3XX_REG_ADDR(0x010e)
0065 #define IOP3XX_ATUBIST      (volatile u8  *)IOP3XX_REG_ADDR(0x010f)
0066 #define IOP3XX_IABAR0       (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
0067 #define IOP3XX_IAUBAR0      (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
0068 #define IOP3XX_IABAR1       (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
0069 #define IOP3XX_IAUBAR1      (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
0070 #define IOP3XX_IABAR2       (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
0071 #define IOP3XX_IAUBAR2      (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
0072 #define IOP3XX_ASVIR        (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
0073 #define IOP3XX_ASIR     (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
0074 #define IOP3XX_ERBAR        (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
0075 #define IOP3XX_ATUILR       (volatile u8  *)IOP3XX_REG_ADDR(0x013c)
0076 #define IOP3XX_ATUIPR       (volatile u8  *)IOP3XX_REG_ADDR(0x013d)
0077 #define IOP3XX_ATUMGNT      (volatile u8  *)IOP3XX_REG_ADDR(0x013e)
0078 #define IOP3XX_ATUMLAT      (volatile u8  *)IOP3XX_REG_ADDR(0x013f)
0079 #define IOP3XX_IALR0        (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
0080 #define IOP3XX_IATVR0       (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
0081 #define IOP3XX_ERLR     (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
0082 #define IOP3XX_ERTVR        (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
0083 #define IOP3XX_IALR1        (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
0084 #define IOP3XX_IALR2        (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
0085 #define IOP3XX_IATVR2       (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
0086 #define IOP3XX_OIOWTVR      (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
0087 #define IOP3XX_OMWTVR0      (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
0088 #define IOP3XX_OUMWTVR0     (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
0089 #define IOP3XX_OMWTVR1      (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
0090 #define IOP3XX_OUMWTVR1     (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
0091 #define IOP3XX_OUDWTVR      (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
0092 #define IOP3XX_ATUCR        (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
0093 #define IOP3XX_PCSR     (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
0094 #define IOP3XX_ATUISR       (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
0095 #define IOP3XX_ATUIMR       (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
0096 #define IOP3XX_IABAR3       (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
0097 #define IOP3XX_IAUBAR3      (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
0098 #define IOP3XX_IALR3        (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
0099 #define IOP3XX_IATVR3       (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
0100 #define IOP3XX_OCCAR        (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
0101 #define IOP3XX_OCCDR        (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
0102 #define IOP3XX_PDSCR        (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
0103 #define IOP3XX_PMCAPID      (volatile u8  *)IOP3XX_REG_ADDR(0x01c0)
0104 #define IOP3XX_PMNEXT       (volatile u8  *)IOP3XX_REG_ADDR(0x01c1)
0105 #define IOP3XX_APMCR        (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
0106 #define IOP3XX_APMCSR       (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
0107 #define IOP3XX_PCIXCAPID    (volatile u8  *)IOP3XX_REG_ADDR(0x01e0)
0108 #define IOP3XX_PCIXNEXT     (volatile u8  *)IOP3XX_REG_ADDR(0x01e1)
0109 #define IOP3XX_PCIXCMD      (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
0110 #define IOP3XX_PCIXSR       (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
0111 #define IOP3XX_PCIIRSR      (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
0112 #define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
0113 #define IOP3XX_PCSR_IN_Q_BUSY   (1 << 14)
0114 #define IOP3XX_ATUCR_OUT_EN (1 << 1)
0115 
0116 #define IOP3XX_INIT_ATU_DEFAULT 0
0117 #define IOP3XX_INIT_ATU_DISABLE -1
0118 #define IOP3XX_INIT_ATU_ENABLE   1
0119 
0120 /* Messaging Unit  */
0121 #define IOP3XX_IMR0     (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
0122 #define IOP3XX_IMR1     (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
0123 #define IOP3XX_OMR0     (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
0124 #define IOP3XX_OMR1     (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
0125 #define IOP3XX_IDR      (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
0126 #define IOP3XX_IISR     (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
0127 #define IOP3XX_IIMR     (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
0128 #define IOP3XX_ODR      (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
0129 #define IOP3XX_OISR     (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
0130 #define IOP3XX_OIMR     (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
0131 #define IOP3XX_MUCR     (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
0132 #define IOP3XX_QBAR     (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
0133 #define IOP3XX_IFHPR        (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
0134 #define IOP3XX_IFTPR        (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
0135 #define IOP3XX_IPHPR        (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
0136 #define IOP3XX_IPTPR        (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
0137 #define IOP3XX_OFHPR        (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
0138 #define IOP3XX_OFTPR        (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
0139 #define IOP3XX_OPHPR        (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
0140 #define IOP3XX_OPTPR        (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
0141 #define IOP3XX_IAR      (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
0142 
0143 /* DMA Controller  */
0144 #define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \
0145                     (0x400 + (chan << 6)))
0146 #define IOP3XX_DMA_UPPER_PA(chan)  (IOP3XX_DMA_PHYS_BASE(chan) + 0x27)
0147 
0148 /* Peripheral bus interface  */
0149 #define IOP3XX_PBCR     (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
0150 #define IOP3XX_PBISR        (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
0151 #define IOP3XX_PBBAR0       (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
0152 #define IOP3XX_PBLR0        (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
0153 #define IOP3XX_PBBAR1       (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
0154 #define IOP3XX_PBLR1        (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
0155 #define IOP3XX_PBBAR2       (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
0156 #define IOP3XX_PBLR2        (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
0157 #define IOP3XX_PBBAR3       (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
0158 #define IOP3XX_PBLR3        (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
0159 #define IOP3XX_PBBAR4       (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
0160 #define IOP3XX_PBLR4        (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
0161 #define IOP3XX_PBBAR5       (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
0162 #define IOP3XX_PBLR5        (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
0163 #define IOP3XX_PMBR0        (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
0164 #define IOP3XX_PMBR1        (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
0165 #define IOP3XX_PMBR2        (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
0166 
0167 /* Peripheral performance monitoring unit  */
0168 #define IOP3XX_GTMR     (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
0169 #define IOP3XX_ESR      (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
0170 #define IOP3XX_EMISR        (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
0171 #define IOP3XX_GTSR     (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
0172 /* PERCR0 DOESN'T EXIST - index from 1! */
0173 #define IOP3XX_PERCR0       (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
0174 
0175 /* Timers  */
0176 #define IOP3XX_TU_TMR0      (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
0177 #define IOP3XX_TU_TMR1      (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
0178 #define IOP3XX_TU_TCR0      (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
0179 #define IOP3XX_TU_TCR1      (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
0180 #define IOP3XX_TU_TRR0      (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
0181 #define IOP3XX_TU_TRR1      (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
0182 #define IOP3XX_TU_TISR      (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
0183 #define IOP3XX_TU_WDTCR     (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
0184 #define IOP_TMR_EN      0x02
0185 #define IOP_TMR_RELOAD      0x04
0186 #define IOP_TMR_PRIVILEGED 0x08
0187 #define IOP_TMR_RATIO_1_1  0x00
0188 
0189 /* Watchdog timer definitions */
0190 #define IOP_WDTCR_EN_ARM        0x1e1e1e1e
0191 #define IOP_WDTCR_EN            0xe1e1e1e1
0192 /* iop3xx does not support stopping the watchdog, so we just re-arm */
0193 #define IOP_WDTCR_DIS_ARM   (IOP_WDTCR_EN_ARM)
0194 #define IOP_WDTCR_DIS       (IOP_WDTCR_EN)
0195 
0196 /* Application accelerator unit  */
0197 #define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
0198 #define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)
0199 
0200 /* I2C bus interface unit  */
0201 #define IOP3XX_ICR0     (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
0202 #define IOP3XX_ISR0     (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
0203 #define IOP3XX_ISAR0        (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
0204 #define IOP3XX_IDBR0        (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
0205 #define IOP3XX_IBMR0        (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
0206 #define IOP3XX_ICR1     (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
0207 #define IOP3XX_ISR1     (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
0208 #define IOP3XX_ISAR1        (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
0209 #define IOP3XX_IDBR1        (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
0210 #define IOP3XX_IBMR1        (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
0211 
0212 
0213 /*
0214  * IOP3XX I/O and Mem space regions for PCI autoconfiguration
0215  */
0216 #define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
0217 #define IOP3XX_PCI_MEM_WINDOW_SIZE  0x08000000
0218 
0219 #define IOP3XX_PCI_LOWER_IO_PA      0x90000000
0220 #define IOP3XX_PCI_LOWER_IO_BA      0x00000000
0221 
0222 #ifndef __ASSEMBLY__
0223 
0224 #include <linux/types.h>
0225 #include <linux/reboot.h>
0226 
0227 void iop3xx_map_io(void);
0228 void iop_enable_cp6(void);
0229 void iop_init_cp6_handler(void);
0230 void iop_init_time(unsigned long tickrate);
0231 void iop3xx_restart(enum reboot_mode, const char *);
0232 
0233 static inline u32 read_tmr0(void)
0234 {
0235     u32 val;
0236     asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val));
0237     return val;
0238 }
0239 
0240 static inline void write_tmr0(u32 val)
0241 {
0242     asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
0243 }
0244 
0245 static inline void write_tmr1(u32 val)
0246 {
0247     asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
0248 }
0249 
0250 static inline u32 read_tcr0(void)
0251 {
0252     u32 val;
0253     asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
0254     return val;
0255 }
0256 
0257 static inline void write_tcr0(u32 val)
0258 {
0259     asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val));
0260 }
0261 
0262 static inline u32 read_tcr1(void)
0263 {
0264     u32 val;
0265     asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
0266     return val;
0267 }
0268 
0269 static inline void write_tcr1(u32 val)
0270 {
0271     asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val));
0272 }
0273 
0274 static inline void write_trr0(u32 val)
0275 {
0276     asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
0277 }
0278 
0279 static inline void write_trr1(u32 val)
0280 {
0281     asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
0282 }
0283 
0284 static inline void write_tisr(u32 val)
0285 {
0286     asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
0287 }
0288 
0289 static inline u32 read_wdtcr(void)
0290 {
0291     u32 val;
0292     asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val));
0293     return val;
0294 }
0295 static inline void write_wdtcr(u32 val)
0296 {
0297     asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val));
0298 }
0299 
0300 extern unsigned long get_iop_tick_rate(void);
0301 
0302 /* only iop13xx has these registers, we define these to present a
0303  * common register interface for the iop_wdt driver.
0304  */
0305 #define IOP_RCSR_WDT    (0)
0306 static inline u32 read_rcsr(void)
0307 {
0308     return 0;
0309 }
0310 static inline void write_wdtsr(u32 val)
0311 {
0312     do { } while (0);
0313 }
0314 
0315 extern struct platform_device iop3xx_dma_0_channel;
0316 extern struct platform_device iop3xx_dma_1_channel;
0317 extern struct platform_device iop3xx_aau_channel;
0318 extern struct platform_device iop3xx_i2c0_device;
0319 extern struct platform_device iop3xx_i2c1_device;
0320 extern struct gpiod_lookup_table iop3xx_i2c0_gpio_lookup;
0321 extern struct gpiod_lookup_table iop3xx_i2c1_gpio_lookup;
0322 
0323 #endif
0324 
0325 
0326 #endif
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